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https://github.com/openwrt/openwrt.git
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c764b2b531
Refreshed all patches. Compile-tested on: ar71xx, cns3xxx, imx6, x86_64 Runtime-tested on: ar71xx, cns3xxx, imx6, x86_64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
211 lines
6.2 KiB
Diff
211 lines
6.2 KiB
Diff
From e74caf41aec5338b8cbbd0a1483650848f16f532 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 16 Jul 2017 12:23:47 +0200
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Subject: [PATCH V2 1/8] MIPS: BCM63XX: add clkdev lookup support
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Enable clkdev lookup support to allow us providing clocks under
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different names to devices more easily, so we don't need to care
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about clock name clashes anymore.
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Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/Kconfig | 1 +
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arch/mips/bcm63xx/clk.c | 150 +++++++++++++++++++++++++++++++++++++-----------
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2 files changed, 116 insertions(+), 35 deletions(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -279,6 +279,7 @@ config BCM63XX
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select GPIOLIB
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select HAVE_CLK
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select MIPS_L1_CACHE_SHIFT_4
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+ select CLKDEV_LOOKUP
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help
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Support for BCM63XX based boards
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -11,6 +11,7 @@
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#include <linux/mutex.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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+#include <linux/clkdev.h>
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#include <linux/delay.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_io.h>
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@@ -359,44 +360,103 @@ long clk_round_rate(struct clk *clk, uns
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}
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EXPORT_SYMBOL_GPL(clk_round_rate);
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-struct clk *clk_get(struct device *dev, const char *id)
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-{
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- if (!strcmp(id, "enet0"))
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- return &clk_enet0;
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- if (!strcmp(id, "enet1"))
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- return &clk_enet1;
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- if (!strcmp(id, "enetsw"))
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- return &clk_enetsw;
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- if (!strcmp(id, "ephy"))
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- return &clk_ephy;
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- if (!strcmp(id, "usbh"))
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- return &clk_usbh;
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- if (!strcmp(id, "usbd"))
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- return &clk_usbd;
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- if (!strcmp(id, "spi"))
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- return &clk_spi;
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- if (!strcmp(id, "hsspi"))
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- return &clk_hsspi;
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- if (!strcmp(id, "xtm"))
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- return &clk_xtm;
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- if (!strcmp(id, "periph"))
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- return &clk_periph;
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- if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
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- return &clk_pcm;
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- if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
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- return &clk_ipsec;
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- if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
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- return &clk_pcie;
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- return ERR_PTR(-ENOENT);
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-}
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-
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-EXPORT_SYMBOL(clk_get);
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-
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-void clk_put(struct clk *clk)
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-{
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-}
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-
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-EXPORT_SYMBOL(clk_put);
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+static struct clk_lookup bcm3368_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "spi", &clk_spi),
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+ CLKDEV_INIT(NULL, "pcm", &clk_pcm),
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+};
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+
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+static struct clk_lookup bcm6328_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
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+ CLKDEV_INIT(NULL, "pcie", &clk_pcie),
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+};
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+
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+static struct clk_lookup bcm6338_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "spi", &clk_spi),
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+};
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+
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+static struct clk_lookup bcm6345_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "spi", &clk_spi),
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+};
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+
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+static struct clk_lookup bcm6348_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "spi", &clk_spi),
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+};
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+
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+static struct clk_lookup bcm6358_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enet0", &clk_enet0),
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+ CLKDEV_INIT(NULL, "enet1", &clk_enet1),
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+ CLKDEV_INIT(NULL, "ephy", &clk_ephy),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "spi", &clk_spi),
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+ CLKDEV_INIT(NULL, "pcm", &clk_pcm),
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+};
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+
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+static struct clk_lookup bcm6362_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "spi", &clk_spi),
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+ CLKDEV_INIT(NULL, "hsspi", &clk_hsspi),
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+ CLKDEV_INIT(NULL, "pcie", &clk_pcie),
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+ CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
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+};
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+
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+static struct clk_lookup bcm6368_clks[] = {
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+ /* fixed rate clocks */
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+ CLKDEV_INIT(NULL, "periph", &clk_periph),
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+ /* gated clocks */
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+ CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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+ CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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+ CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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+ CLKDEV_INIT(NULL, "spi", &clk_spi),
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+ CLKDEV_INIT(NULL, "xtm", &clk_xtm),
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+ CLKDEV_INIT(NULL, "ipsec", &clk_ipsec),
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+};
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#define HSSPI_PLL_HZ_6328 133333333
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#define HSSPI_PLL_HZ_6362 400000000
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@@ -404,11 +464,31 @@ EXPORT_SYMBOL(clk_put);
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static int __init bcm63xx_clk_init(void)
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{
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switch (bcm63xx_get_cpu_id()) {
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+ case BCM3368_CPU_ID:
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+ clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));
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+ break;
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case BCM6328_CPU_ID:
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clk_hsspi.rate = HSSPI_PLL_HZ_6328;
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+ clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));
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+ break;
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+ case BCM6338_CPU_ID:
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+ clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks));
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+ break;
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+ case BCM6345_CPU_ID:
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+ clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks));
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+ break;
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+ case BCM6348_CPU_ID:
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+ clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks));
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+ break;
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+ case BCM6358_CPU_ID:
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+ clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks));
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break;
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case BCM6362_CPU_ID:
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clk_hsspi.rate = HSSPI_PLL_HZ_6362;
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+ clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks));
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+ break;
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+ case BCM6368_CPU_ID:
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+ clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));
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break;
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}
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