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https://github.com/openwrt/openwrt.git
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e39414ed07
Refreshed all patches Dropped upstreamed patches: 522-PCI-aardvark-fix-logic-in-PCI-configuration-read-write-functions.patch 523-PCI-aardvark-set-PIO_ADDR_LS-correctly-in-advk_pcie_rd_conf.patch 525-PCI-aardvark-use-isr1-instead-of-isr0-interrupt-in-legacy-irq-mode.patch 527-PCI-aardvark-fix-PCIe-max-read-request-size-setting.patch updated patches: 524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch 030-USB-serial-option-fix-dwm-158-3g-modem-interface.patch Added new ARM64 symbol: CONFIG_ARM64_ERRATUM_1024718 Compile-tested on: cns3xxx, imx6, mvebu (arm64), x86_64 Runtime-tested on: cns3xxx, imx6, x86_64 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
117 lines
3.0 KiB
Diff
117 lines
3.0 KiB
Diff
From 6d5af7093aea4f18e040e73db2ad99aaa0c0f77e Mon Sep 17 00:00:00 2001
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From: Linus Walleij <linus.walleij@linaro.org>
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Date: Sun, 19 Nov 2017 11:04:23 +0100
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Subject: [PATCH] ARM: dts: Add ethernet to a bunch of platforms
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These platforms have the PHY defined already so we just
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need to add a single device node to each of them to activate
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the ethernet device.
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The PHY skew/delay settings for pin control is known from a
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few vendor trees and old OpenWRT patch sets.
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This is a modified version of upstream commit
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95220046a62c00b5afb1aa7c1971989d427db977,
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just dropping the NAS4220B changes.
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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arch/arm/boot/dts/gemini-dlink-dns-313.dts | 62 ++++++++++++++++++++++++++++++
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arch/arm/boot/dts/gemini-wbd222.dts | 7 ++++
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2 files changed, 69 insertions(+)
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--- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts
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+++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts
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@@ -215,6 +215,56 @@
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groups = "gpio1dgrp";
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};
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};
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+ pinctrl-gmii {
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+ mux {
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+ function = "gmii";
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+ groups = "gmii_gmac0_grp";
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+ };
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+ /*
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+ * In the vendor Linux tree, these values are set for the C3
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+ * version of the SL3512 ASIC with the comment "benson suggest"
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+ */
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+ conf0 {
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+ pins = "R8 GMAC0 RXDV", "U11 GMAC1 RXDV";
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+ skew-delay = <0>;
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+ };
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+ conf1 {
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+ pins = "T8 GMAC0 RXC";
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+ skew-delay = <10>;
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+ };
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+ conf2 {
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+ pins = "T11 GMAC1 RXC";
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+ skew-delay = <15>;
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+ };
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+ conf3 {
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+ pins = "P8 GMAC0 TXEN", "V11 GMAC1 TXEN";
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+ skew-delay = <7>;
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+ };
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+ conf4 {
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+ pins = "V7 GMAC0 TXC", "P10 GMAC1 TXC";
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+ skew-delay = <10>;
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+ };
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+ conf5 {
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+ /* The data lines all have default skew */
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+ pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
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+ "P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
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+ "R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
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+ "V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
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+ "R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
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+ "U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
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+ skew-delay = <7>;
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+ };
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+ conf6 {
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+ pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
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+ "R7 GMAC0 TXD2", "P7 GMAC0 TXD3";
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+ skew-delay = <5>;
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+ };
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+ /* Set up drive strength on GMAC0 to 16 mA */
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+ conf7 {
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+ groups = "gmii_gmac0_grp";
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+ drive-strength = <16>;
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+ };
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+ };
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};
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};
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@@ -235,6 +285,18 @@
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pinctrl-0 = <&gpio1_default_pins>;
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};
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+ ethernet@60000000 {
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+ status = "okay";
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+
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+ ethernet-port@0 {
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+ phy-mode = "rgmii";
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+ phy-handle = <&phy0>;
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+ };
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+ ethernet-port@1 {
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+ /* Not used in this platform */
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+ };
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+ };
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+
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ata@63000000 {
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status = "okay";
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};
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--- a/arch/arm/boot/dts/gemini-wbd222.dts
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+++ b/arch/arm/boot/dts/gemini-wbd222.dts
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@@ -136,6 +136,13 @@
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"gpio0bgrp";
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};
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};
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+ pinctrl-gmii {
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+ /* This platform use both the ethernet ports */
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+ mux {
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+ function = "gmii";
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+ groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
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+ };
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+ };
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};
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};
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