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58f4667a37
New stm32 target introduces support for stm32mp1 based devices.
For now it includes an initial support of the STM32MP135F-DK device.
The specifications bellow only list supported features.
Specifications
--------------
SOC: STM32MP135FAF7
RAM: 512 MiB
Storage: SD Card
Ethernet: 2x 100 Mbps
Wireless: 2.4GHz Cypress CYW43455 (802.11b/g/n)
LEDs: Heartbeat (Blue)
Buttons: 1x Reset, 1x User (USER2)
USB: 4x 2.0 Type-A
Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/16716
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 851e7f77e4)
Link: https://github.com/openwrt/openwrt/pull/17097
Signed-off-by: Petr Štetiar <ynezz@true.cz>
109 lines
2.9 KiB
Diff
109 lines
2.9 KiB
Diff
From fcf6ca2da4650d0a7a9cd62c8c72341860931159 Mon Sep 17 00:00:00 2001
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From: Christophe Roullier <christophe.roullier@foss.st.com>
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Date: Mon, 10 Jun 2024 10:03:07 +0200
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Subject: [PATCH 4/5] ARM: dts: stm32: add ethernet1 and ethernet2 support on
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stm32mp13
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Both instances ethernet based on GMAC SNPS IP on stm32mp13.
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GMAC IP version is SNPS 4.20.
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Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
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Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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---
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arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++
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arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++
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2 files changed, 69 insertions(+)
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--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
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+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
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@@ -883,6 +883,12 @@
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ts_cal2: calib@5e {
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reg = <0x5e 0x2>;
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};
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+ ethernet_mac1_address: mac1@e4 {
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+ reg = <0xe4 0x6>;
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+ };
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+ ethernet_mac2_address: mac2@ea {
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+ reg = <0xea 0x6>;
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+ };
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};
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etzpc: bus@5c007000 {
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@@ -1409,6 +1415,38 @@
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status = "disabled";
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};
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+ ethernet1: ethernet@5800a000 {
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+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
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+ reg = <0x5800a000 0x2000>;
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+ reg-names = "stmmaceth";
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+ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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+ <&exti 68 1>;
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+ interrupt-names = "macirq", "eth_wake_irq";
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+ clock-names = "stmmaceth",
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+ "mac-clk-tx",
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+ "mac-clk-rx",
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+ "ethstp",
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+ "eth-ck";
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+ clocks = <&rcc ETH1MAC>,
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+ <&rcc ETH1TX>,
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+ <&rcc ETH1RX>,
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+ <&rcc ETH1STP>,
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+ <&rcc ETH1CK_K>;
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+ st,syscon = <&syscfg 0x4 0xff0000>;
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+ snps,mixed-burst;
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+ snps,pbl = <2>;
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+ snps,axi-config = <&stmmac_axi_config_1>;
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+ snps,tso;
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+ access-controllers = <&etzpc 48>;
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+ status = "disabled";
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+
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+ stmmac_axi_config_1: stmmac-axi-config {
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+ snps,blen = <0 0 0 0 16 8 4>;
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+ snps,rd_osr_lmt = <0x7>;
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+ snps,wr_osr_lmt = <0x7>;
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+ };
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+ };
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+
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usbphyc: usbphyc@5a006000 {
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#address-cells = <1>;
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#size-cells = <0>;
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--- a/arch/arm/boot/dts/st/stm32mp133.dtsi
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+++ b/arch/arm/boot/dts/st/stm32mp133.dtsi
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@@ -68,4 +68,35 @@
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};
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};
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};
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+
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+ ethernet2: ethernet@5800e000 {
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+ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a";
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+ reg = <0x5800e000 0x2000>;
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+ reg-names = "stmmaceth";
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+ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+ clock-names = "stmmaceth",
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+ "mac-clk-tx",
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+ "mac-clk-rx",
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+ "ethstp",
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+ "eth-ck";
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+ clocks = <&rcc ETH2MAC>,
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+ <&rcc ETH2TX>,
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+ <&rcc ETH2RX>,
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+ <&rcc ETH2STP>,
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+ <&rcc ETH2CK_K>;
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+ st,syscon = <&syscfg 0x4 0xff000000>;
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+ snps,mixed-burst;
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+ snps,pbl = <2>;
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+ snps,axi-config = <&stmmac_axi_config_2>;
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+ snps,tso;
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+ access-controllers = <&etzpc 49>;
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+ status = "disabled";
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+
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+ stmmac_axi_config_2: stmmac-axi-config {
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+ snps,blen = <0 0 0 0 16 8 4>;
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+ snps,rd_osr_lmt = <0x7>;
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+ snps,wr_osr_lmt = <0x7>;
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+ };
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+ };
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};
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