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2e715fb4fc
Add support for BCM2712 (Raspberry Pi 5).
3bb5880ab3
Patches were generated from the diff between linux kernel branch linux-6.1.y
and rpi-6.1.y from raspberry pi kernel source:
- git format-patch linux-6.1.y...rpi-6.1.y
Build system: x86_64
Build-tested: bcm2708, bcm2709, bcm2710, bcm2711
Run-tested: bcm2710/RPi3B, bcm2711/RPi4B
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[Remove applied and reverted patches, squash patches and config commits]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
75 lines
1.9 KiB
Diff
75 lines
1.9 KiB
Diff
From 72bfb10c9393688d00e4e0b00d416e23c2753318 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 17 Feb 2023 15:07:29 +0100
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Subject: [PATCH] drm/vc4: hvs: Use switch statement to simplify
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enabling/disabling irq
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Since we'll support BCM2712 soon, let's move the logic to enable and
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disable the end-of-frame interrupts to a switch to extend it more
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easily.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 42 ++++++++++++++++++++++++++---------
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1 file changed, 32 insertions(+), 10 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -416,24 +416,46 @@ static void vc4_hvs_irq_enable_eof(const
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unsigned int channel)
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{
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struct vc4_dev *vc4 = hvs->vc4;
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- u32 irq_mask = vc4->gen == VC4_GEN_5 ?
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- SCALER5_DISPCTRL_DSPEIEOF(channel) :
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- SCALER_DISPCTRL_DSPEIEOF(channel);
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- HVS_WRITE(SCALER_DISPCTRL,
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- HVS_READ(SCALER_DISPCTRL) | irq_mask);
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+ switch (vc4->gen) {
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+ case VC4_GEN_4:
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+ HVS_WRITE(SCALER_DISPCTRL,
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+ HVS_READ(SCALER_DISPCTRL) |
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+ SCALER_DISPCTRL_DSPEIEOF(channel));
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+ break;
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+
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+ case VC4_GEN_5:
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+ HVS_WRITE(SCALER_DISPCTRL,
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+ HVS_READ(SCALER_DISPCTRL) |
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+ SCALER5_DISPCTRL_DSPEIEOF(channel));
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+ break;
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+
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+ default:
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+ break;
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+ }
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}
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static void vc4_hvs_irq_clear_eof(const struct vc4_hvs *hvs,
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unsigned int channel)
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{
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struct vc4_dev *vc4 = hvs->vc4;
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- u32 irq_mask = vc4->gen == VC4_GEN_5 ?
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- SCALER5_DISPCTRL_DSPEIEOF(channel) :
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- SCALER_DISPCTRL_DSPEIEOF(channel);
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- HVS_WRITE(SCALER_DISPCTRL,
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- HVS_READ(SCALER_DISPCTRL) & ~irq_mask);
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+ switch (vc4->gen) {
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+ case VC4_GEN_4:
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+ HVS_WRITE(SCALER_DISPCTRL,
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+ HVS_READ(SCALER_DISPCTRL) &
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+ ~SCALER_DISPCTRL_DSPEIEOF(channel));
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+ break;
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+
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+ case VC4_GEN_5:
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+ HVS_WRITE(SCALER_DISPCTRL,
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+ HVS_READ(SCALER_DISPCTRL) &
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+ ~SCALER5_DISPCTRL_DSPEIEOF(channel));
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+ break;
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+
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+ default:
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+ break;
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+ }
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}
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static struct vc4_hvs_dlist_allocation *
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