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793f8ab62c
Add kernel patches for version 6.1. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
105 lines
3.6 KiB
Diff
105 lines
3.6 KiB
Diff
From 3bd2ed90a679b87d4dc3fe0a70a83c323df915de Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Wed, 11 Jan 2023 17:30:58 +0000
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Subject: [PATCH] vc4/hdmi: Always enable GCP with AVMUTE cleared
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See: https://forum.libreelec.tv/thread/24780-le-10-0-1-rpi4-no-picture-after-update-from-le-10-0-0
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Issue is some displays go blank at the point of firmware to kms handover.
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Plugging/unplugging hdmi cable, power cycling display, or switching standby off/on
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typically resolve this case.
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Finally managed to find a display that suffers from this, and track down the issue.
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The firmware uses AVMUTE in normal operation. It will set AVMUTE before disabling hdmi
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clocks and phy. It will clear AVMUTE after clocks and phy are set up for a new hdmi mode.
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But with the hdmi handover from firmware to kms, AVMUTE will be set by firmware.
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kms driver typically has no GCP packet (except for deep colour modes).
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The spec isn't clear on whether to consider the AVMUTE as continuing indefinitely
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in the absense of a GCP packet, or to consider that state to have ended.
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Most displays behave as we want, but there are a number (from mutiple manufacturers)
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which need to see AVMUTE cleared before displaying a picture.
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Lets just always enable GCP packet with AVMUTE cleared. That resolves the issue on
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problematic displays.
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From HDMI 1.4 spec:
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A CD field of zero (Color Depth not indicated) shall be used whenever the Sink does
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not indicate support for Deep Color. This value may also be used in Deep Color mode
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to transmit a GCP indicating only non-Deep Color information (e.g. AVMUTE).
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So use CD=0 where we were previously not enabling a GCP.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 18 +++++++++---------
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1 file changed, 9 insertions(+), 9 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -107,6 +107,10 @@
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#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
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#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
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+#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0)
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+#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0)
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+#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4)
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+
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# define VC4_HD_M_SW_RST BIT(2)
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# define VC4_HD_M_ENABLE BIT(0)
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@@ -1559,7 +1563,6 @@ static void vc5_hdmi_set_timings(struct
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VC4_HDMI_VERTB_VBP));
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unsigned long flags;
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unsigned char gcp;
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- bool gcp_en;
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u32 reg;
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int idx;
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@@ -1594,16 +1597,13 @@ static void vc5_hdmi_set_timings(struct
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switch (vc4_state->output_bpc) {
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case 12:
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gcp = 6;
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- gcp_en = true;
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break;
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case 10:
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gcp = 5;
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- gcp_en = true;
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break;
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case 8:
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default:
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- gcp = 4;
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- gcp_en = false;
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+ gcp = 0;
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break;
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}
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@@ -1612,8 +1612,7 @@ static void vc5_hdmi_set_timings(struct
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* doesn't signal in GCP.
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*/
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if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
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- gcp = 4;
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- gcp_en = false;
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+ gcp = 0;
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}
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reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
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@@ -1626,11 +1625,12 @@ static void vc5_hdmi_set_timings(struct
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reg = HDMI_READ(HDMI_GCP_WORD_1);
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reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
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reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
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+ reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK;
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+ reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE;
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HDMI_WRITE(HDMI_GCP_WORD_1, reg);
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reg = HDMI_READ(HDMI_GCP_CONFIG);
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- reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
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- reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
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+ reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
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HDMI_WRITE(HDMI_GCP_CONFIG, reg);
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reg = HDMI_READ(HDMI_MISC_CONTROL);
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