mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
793f8ab62c
Add kernel patches for version 6.1. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
35 lines
992 B
Diff
35 lines
992 B
Diff
From abd81cbef43375bdca1414bb97960161e7a8fe49 Mon Sep 17 00:00:00 2001
|
|
From: Dom Cobley <popcornmix@gmail.com>
|
|
Date: Tue, 19 Oct 2021 14:14:55 +0100
|
|
Subject: [PATCH] clk-bcm2835: Remove VEC clock support
|
|
|
|
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
|
|
---
|
|
drivers/clk/bcm/clk-bcm2835.c | 15 ---------------
|
|
1 file changed, 15 deletions(-)
|
|
|
|
--- a/drivers/clk/bcm/clk-bcm2835.c
|
|
+++ b/drivers/clk/bcm/clk-bcm2835.c
|
|
@@ -2238,21 +2238,6 @@ static const struct bcm2835_clk_desc clk
|
|
.tcnt_mux = 28,
|
|
.round_up = true),
|
|
|
|
- /* TV encoder clock. Only operating frequency is 108Mhz. */
|
|
- [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
|
|
- SOC_ALL,
|
|
- .name = "vec",
|
|
- .ctl_reg = CM_VECCTL,
|
|
- .div_reg = CM_VECDIV,
|
|
- .int_bits = 4,
|
|
- .frac_bits = 0,
|
|
- /*
|
|
- * Allow rate change propagation only on PLLH_AUX which is
|
|
- * assigned index 7 in the parent array.
|
|
- */
|
|
- .set_rate_parent = BIT(7),
|
|
- .tcnt_mux = 29),
|
|
-
|
|
/* dsi clocks */
|
|
[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
|
|
SOC_ALL,
|