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b7e9445d6d
Import pending patches adding support for MT7988 and provide builds for the reference board for all possible boot media. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
139 lines
4.1 KiB
Diff
139 lines
4.1 KiB
Diff
From 542d455466bdf32e1bb70230ebcdefd8ed09643b Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 19 Jul 2023 17:17:22 +0800
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Subject: [PATCH 22/29] net: mediatek: add support for GMAC/USB3 PHY mux mode
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for MT7981
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MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
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register must be set to connect the SGMII phy to GMAC2.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/net/mtk_eth.c | 33 ++++++++++++++++++++++++++++++++-
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drivers/net/mtk_eth.h | 16 ++++++++++++++++
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2 files changed, 48 insertions(+), 1 deletion(-)
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--- a/drivers/net/mtk_eth.c
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+++ b/drivers/net/mtk_eth.c
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@@ -103,6 +103,8 @@ struct mtk_eth_priv {
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struct regmap *ethsys_regmap;
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+ struct regmap *infra_regmap;
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+
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struct mii_dev *mdio_bus;
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int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
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int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
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@@ -186,6 +188,17 @@ static void mtk_ethsys_rmw(struct mtk_et
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regmap_write(priv->ethsys_regmap, reg, val);
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}
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+static void mtk_infra_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr,
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+ u32 set)
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+{
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+ uint val;
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+
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+ regmap_read(priv->infra_regmap, reg, &val);
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+ val &= ~clr;
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+ val |= set;
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+ regmap_write(priv->infra_regmap, reg, val);
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+}
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+
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/* Direct MDIO clause 22/45 access via SoC */
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static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data,
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u32 cmd, u32 st)
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@@ -1139,6 +1152,11 @@ static void mtk_mac_init(struct mtk_eth_
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break;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_2500BASEX:
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+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_GMAC2_U3_QPHY)) {
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+ mtk_infra_rmw(priv, USB_PHY_SWITCH_REG, QPHY_SEL_MASK,
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+ SGMII_QPHY_SEL);
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+ }
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+
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ge_mode = GE_MODE_RGMII;
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mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
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SYSCFG0_SGMII_SEL(priv->gmac_id));
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@@ -1497,6 +1515,19 @@ static int mtk_eth_of_to_plat(struct ude
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if (IS_ERR(priv->ethsys_regmap))
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return PTR_ERR(priv->ethsys_regmap);
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+ if (MTK_HAS_CAPS(priv->soc->caps, MTK_INFRA)) {
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+ /* get corresponding infracfg phandle */
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+ ret = dev_read_phandle_with_args(dev, "mediatek,infracfg",
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+ NULL, 0, 0, &args);
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+
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+ if (ret)
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+ return ret;
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+
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+ priv->infra_regmap = syscon_node_to_regmap(args.node);
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+ if (IS_ERR(priv->infra_regmap))
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+ return PTR_ERR(priv->infra_regmap);
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+ }
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+
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/* Reset controllers */
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ret = reset_get_by_name(dev, "fe", &priv->rst_fe);
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if (ret) {
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@@ -1614,7 +1645,7 @@ static const struct mtk_soc_data mt7986_
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};
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static const struct mtk_soc_data mt7981_data = {
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- .caps = MT7986_CAPS,
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+ .caps = MT7981_CAPS,
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.ana_rgc3 = 0x128,
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.pdma_base = PDMA_V2_BASE,
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.txd_size = sizeof(struct mtk_tx_dma_v2),
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--- a/drivers/net/mtk_eth.h
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+++ b/drivers/net/mtk_eth.h
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@@ -15,27 +15,38 @@
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enum mkt_eth_capabilities {
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MTK_TRGMII_BIT,
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MTK_TRGMII_MT7621_CLK_BIT,
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+ MTK_U3_COPHY_V2_BIT,
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+ MTK_INFRA_BIT,
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MTK_NETSYS_V2_BIT,
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/* PATH BITS */
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MTK_ETH_PATH_GMAC1_TRGMII_BIT,
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+ MTK_ETH_PATH_GMAC2_SGMII_BIT,
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};
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#define MTK_TRGMII BIT(MTK_TRGMII_BIT)
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#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
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+#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
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+#define MTK_INFRA BIT(MTK_INFRA_BIT)
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#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
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/* Supported path present on SoCs */
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#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
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+#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
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+
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#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
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+#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA)
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+
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#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
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#define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK)
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#define MT7623_CAPS (MTK_GMAC1_TRGMII)
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+#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2)
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+
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#define MT7986_CAPS (MTK_NETSYS_V2)
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/* Frame Engine Register Bases */
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@@ -56,6 +67,11 @@ enum mkt_eth_capabilities {
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#define ETHSYS_CLKCFG0_REG 0x2c
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#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
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+/* Top misc registers */
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+#define USB_PHY_SWITCH_REG 0x218
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+#define QPHY_SEL_MASK 0x3
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+#define SGMII_QPHY_SEL 0x2
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+
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/* SYSCFG0_GE_MODE: GE Modes */
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#define GE_MODE_RGMII 0
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#define GE_MODE_MII 1
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