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da42c329c6
This patch converts legacy Ralink SoCs and MT7620 WiFi calibration data to NVMEM format. The EEPROM size is 0x200. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
118 lines
2.0 KiB
Plaintext
118 lines
2.0 KiB
Plaintext
#include "mt7620a_lenovo_newifi-y1.dtsi"
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/ {
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compatible = "lenovo,newifi-y1s", "lenovo,newifi-y1", "ralink,mt7620a-soc";
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model = "Lenovo Y1S";
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aliases {
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led-boot = &led_power_blue;
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led-failsafe = &led_power_blue;
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led-running = &led_power_blue;
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led-upgrade = &led_power_blue;
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label-mac-device = ðernet;
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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usb0 {
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gpio-export,name = "usb0";
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gpio-export,output = <1>;
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gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
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};
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usb1 {
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gpio-export,name = "usb1";
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gpio-export,output = <1>;
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gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
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};
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usb2 {
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gpio-export,name = "usb2";
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gpio-export,output = <1>;
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gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
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};
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};
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leds {
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compatible = "gpio-leds";
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power1 {
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label = "yellow:power";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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led_power_blue: power2 {
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label = "blue:power";
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gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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};
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wlan1 {
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label = "yellow:wifi";
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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};
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wlan2 {
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label = "blue:wifi";
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gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
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};
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usb1 {
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label = "yellow:usb";
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gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
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};
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usb2 {
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label = "blue:usb";
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gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ohci_port1>, <&ehci_port1>;
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linux,default-trigger = "usbport";
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};
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internet {
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label = "blue:internet";
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gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
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nvmem-cells = <&macaddr_factory_28>;
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nvmem-cell-names = "mac-address";
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mediatek,portmap = "wllll";
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port@4 {
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status = "okay";
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phy-handle = <&phy4>;
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phy-mode = "rgmii";
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};
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port@5 {
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status = "okay";
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phy-handle = <&phy5>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,port4-gmac;
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mediatek,ephy-base = /bits/ 8 <8>;
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};
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