mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 02:29:01 +00:00
26 lines
1023 B
Diff
26 lines
1023 B
Diff
From 519d0047f84cdd1050418bb86dd34a0c6df1206a Mon Sep 17 00:00:00 2001
|
|
From: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
Date: Wed, 20 Jul 2016 14:32:46 -0400
|
|
Subject: [PATCH] rtl8xxxu: Do not set REG_FPGA0_TX_INFO on 8188eu
|
|
|
|
The vendor driver doesn't set this for 8188eu either. It is unclear if
|
|
this is only relevant for gen1 parts.
|
|
|
|
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
|
|
---
|
|
drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 3 ++-
|
|
1 file changed, 2 insertions(+), 1 deletion(-)
|
|
|
|
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
|
|
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
|
|
@@ -3962,7 +3962,8 @@ static int rtl8xxxu_init_device(struct i
|
|
goto exit;
|
|
|
|
/* RFSW Control - clear bit 14 ?? */
|
|
- if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
|
|
+ if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E &&
|
|
+ priv->rtl_chip != RTL8188E)
|
|
rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
|
|
|
|
val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
|