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f0c740650b
The following patches are dropped because they are now upstreamed:
- 0002-gpio-stp-xway-Implement-get-callback.patch
upstreamed with commit 5b9b2b5284f819 ("gpio: stp-xway: Implement get
callback")
- 0027-01-net-phy-intel-xway-add-VR9-version-number.patch
upstreamed with commit 5b73d9955fb4b0 ("net: phy: intel-xway: add VR9
version number")
- 0027-02-net-phy-intel-xway-add-VR9-v1.1-phy-ids.patch
upstreamed with commit f452518c982e57 ("net: phy: intel-xway: add VR9
v1.1 phy ids")
The following patches were updated:
- 0018-MTD-nand-lots-of-xrx200-fixes.patch
the mainline driver now resides in drivers/mtd/nand/raw/xway_nand.c
(instead of drivers/mtd/nand/xway_nand.c)
- 0025-NET-MIPS-lantiq-adds-xrx200-net.patch
the DMA API now requires a valid device to be passed to all operations
- 0028-NET-lantiq-various-etop-fixes.patch
the DMA API now requires a valid device to be passed to all operations
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Mathias Kresin <dev@kresin.me>
50 lines
1.6 KiB
Diff
50 lines
1.6 KiB
Diff
From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Fri, 6 Jan 2017 17:40:12 +0100
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Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
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This adds code to initialize the USB controller and PHY also on Danube,
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Amazon SE and AR10. This code is based on the Vendor driver from
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different UGW versions and compared to the hardware documentation.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
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2 files changed, 110 insertions(+), 30 deletions(-)
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -246,6 +246,25 @@ static void pmu_disable(struct clk *clk)
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pr_warn("deactivating PMU module failed!");
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}
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+static void usb_set_clock(void)
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+{
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+ unsigned int val = ltq_cgu_r32(ifccr);
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+
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+ if (of_machine_is_compatible("lantiq,ar10") ||
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+ of_machine_is_compatible("lantiq,grx390")) {
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+ val &= ~0x03; /* XTAL divided by 3 */
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+ } else if (of_machine_is_compatible("lantiq,ar9") ||
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+ of_machine_is_compatible("lantiq,vr9")) {
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+ /* TODO: this depends on the XTAL frequency */
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+ val |= 0x03; /* XTAL divided by 3 */
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+ } else if (of_machine_is_compatible("lantiq,ase")) {
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+ val |= 0x20; /* from XTAL */
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+ } else if (of_machine_is_compatible("lantiq,danube")) {
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+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
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+ }
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+ ltq_cgu_w32(val, ifccr);
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+}
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+
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/* the pci enable helper */
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static int pci_enable(struct clk *clk)
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{
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@@ -567,4 +586,5 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
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clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
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}
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+ usb_set_clock();
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}
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