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107 lines
4.3 KiB
Diff
107 lines
4.3 KiB
Diff
From 18f93916e42ea25fc77cab20d1e038620e33d741 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Fri, 28 Sep 2018 16:21:24 -0700
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Subject: [PATCH] drm/v3d: Add a little debugfs entry for measuring the
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core clock.
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This adds just enough performance counter support to measure the
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clock. We don't have linux kernel drivers for the clock driving the
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HW, and this was useful for determining that the V3D HW is running on
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a slow clock, not that the driver was slow.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Link: https://patchwork.freedesktop.org/patch/msgid/20180928232126.4332-2-eric@anholt.net
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Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
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(cherry picked from commit 6915c9a525e575732429c22b28eb11871a29374b)
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---
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drivers/gpu/drm/v3d/v3d_debugfs.c | 35 +++++++++++++++++++++++++++++++
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drivers/gpu/drm/v3d/v3d_regs.h | 30 ++++++++++++++++++++++++++
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2 files changed, 65 insertions(+)
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--- a/drivers/gpu/drm/v3d/v3d_debugfs.c
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+++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
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@@ -179,9 +179,44 @@ static int v3d_debugfs_bo_stats(struct s
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return 0;
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}
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+static int v3d_measure_clock(struct seq_file *m, void *unused)
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+{
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+ struct drm_info_node *node = (struct drm_info_node *)m->private;
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+ struct drm_device *dev = node->minor->dev;
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+ struct v3d_dev *v3d = to_v3d_dev(dev);
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+ uint32_t cycles;
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+ int core = 0;
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+ int measure_ms = 1000;
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+
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+ if (v3d->ver >= 40) {
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+ V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
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+ V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
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+ V3D_PCTR_S0));
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+ V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
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+ V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
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+ } else {
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+ V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
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+ V3D_PCTR_CYCLE_COUNT);
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+ V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
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+ V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
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+ V3D_V3_PCTR_0_EN_ENABLE |
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+ 1);
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+ }
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+ msleep(measure_ms);
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+ cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
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+
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+ seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
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+ cycles,
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+ cycles / (measure_ms * 1000),
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+ (cycles / (measure_ms * 100)) % 10);
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+
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+ return 0;
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+}
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+
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static const struct drm_info_list v3d_debugfs_list[] = {
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{"v3d_ident", v3d_v3d_debugfs_ident, 0},
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{"v3d_regs", v3d_v3d_debugfs_regs, 0},
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+ {"measure_clock", v3d_measure_clock, 0},
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{"bo_stats", v3d_debugfs_bo_stats, 0},
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};
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--- a/drivers/gpu/drm/v3d/v3d_regs.h
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+++ b/drivers/gpu/drm/v3d/v3d_regs.h
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@@ -267,6 +267,36 @@
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# define V3D_PTB_BXCF_RWORDERDISA BIT(1)
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# define V3D_PTB_BXCF_CLIPDISA BIT(0)
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+#define V3D_V3_PCTR_0_EN 0x00674
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+#define V3D_V3_PCTR_0_EN_ENABLE BIT(31)
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+#define V3D_V4_PCTR_0_EN 0x00650
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+/* When a bit is set, resets the counter to 0. */
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+#define V3D_V3_PCTR_0_CLR 0x00670
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+#define V3D_V4_PCTR_0_CLR 0x00654
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+#define V3D_PCTR_0_OVERFLOW 0x00658
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+
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+#define V3D_V3_PCTR_0_PCTRS0 0x00684
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+#define V3D_V3_PCTR_0_PCTRS15 0x00660
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+#define V3D_V3_PCTR_0_PCTRSX(x) (V3D_V3_PCTR_0_PCTRS0 + \
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+ 4 * (x))
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+/* Each src reg muxes four counters each. */
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+#define V3D_V4_PCTR_0_SRC_0_3 0x00660
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+#define V3D_V4_PCTR_0_SRC_28_31 0x0067c
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+# define V3D_PCTR_S0_MASK V3D_MASK(6, 0)
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+# define V3D_PCTR_S0_SHIFT 0
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+# define V3D_PCTR_S1_MASK V3D_MASK(14, 8)
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+# define V3D_PCTR_S1_SHIFT 8
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+# define V3D_PCTR_S2_MASK V3D_MASK(22, 16)
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+# define V3D_PCTR_S2_SHIFT 16
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+# define V3D_PCTR_S3_MASK V3D_MASK(30, 24)
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+# define V3D_PCTR_S3_SHIFT 24
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+# define V3D_PCTR_CYCLE_COUNT 32
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+
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+/* Output values of the counters. */
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+#define V3D_PCTR_0_PCTR0 0x00680
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+#define V3D_PCTR_0_PCTR31 0x006fc
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+#define V3D_PCTR_0_PCTRX(x) (V3D_PCTR_0_PCTR0 + \
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+ 4 * (x))
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#define V3D_GMP_STATUS 0x00800
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# define V3D_GMP_STATUS_GMPRST BIT(31)
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# define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24)
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