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170 lines
5.5 KiB
Diff
170 lines
5.5 KiB
Diff
From 28758a9da77954ed323f86123ef448c6a563c037 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Mon, 28 Jan 2013 20:06:22 +0100
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Subject: [PATCH 04/11] MIPS: BCM63XX: add OHCI/EHCI configuration bits to
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common USB code
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This patch updates the common USB code touching the USB private
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registers with the specific bits to properly enable OHCI and EHCI
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controllers on BCM63xx SoCs. As a result we now need to protect access
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to Read Modify Write sequences using a spinlock because we cannot
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guarantee that any of the exposed helper will not be called
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concurrently.
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Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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---
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arch/mips/bcm63xx/usb-common.c | 97 ++++++++++++++++++++
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.../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h | 2 +
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2 files changed, 99 insertions(+)
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--- a/arch/mips/bcm63xx/usb-common.c
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+++ b/arch/mips/bcm63xx/usb-common.c
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@@ -5,10 +5,12 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
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* Copyright (C) 2012 Broadcom Corporation
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*
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*/
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+#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <bcm63xx_cpu.h>
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@@ -16,9 +18,14 @@
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#include <bcm63xx_io.h>
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#include <bcm63xx_usb_priv.h>
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+static DEFINE_SPINLOCK(usb_priv_reg_lock);
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+
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void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device)
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{
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u32 val;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&usb_priv_reg_lock, flags);
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val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
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if (is_device) {
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@@ -36,12 +43,17 @@ void bcm63xx_usb_priv_select_phy_mode(u3
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else
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val &= ~USBH_PRIV_SWAP_USBD_MASK;
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bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);
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+
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+ spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
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}
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EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode);
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void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on)
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{
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u32 val;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&usb_priv_reg_lock, flags);
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val = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);
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if (is_on)
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@@ -49,5 +61,90 @@ void bcm63xx_usb_priv_select_pullup(u32
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else
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val |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);
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bcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);
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+
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+ spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
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}
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EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup);
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+
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+/* The following array represents the meaning of the DESC/DATA
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+ * endian swapping with respect to the CPU configured endianness
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+ *
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+ * DATA ENDN mmio descriptor
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+ * 0 0 BE invalid
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+ * 0 1 BE LE
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+ * 1 0 BE BE
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+ * 1 1 BE invalid
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+ *
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+ * Since BCM63XX SoCs are configured to be in big-endian mode
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+ * we want configuration at line 3.
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+ */
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+void bcm63xx_usb_priv_ohci_cfg_set(void)
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+{
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+ u32 reg;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&usb_priv_reg_lock, flags);
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+
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+ if (BCMCPU_IS_6348())
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+ bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG);
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+ else if (BCMCPU_IS_6358()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);
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+ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);
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+ /*
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+ * The magic value comes for the original vendor BSP
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+ * and is needed for USB to work. Datasheet does not
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+ * help, so the magic value is used as-is.
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+ */
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+ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
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+ USBH_PRIV_TEST_6358_REG);
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+
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+ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
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+ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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+ reg |= USBH_PRIV_SETUP_IOC_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+ }
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+
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+ spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
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+}
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+
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+void bcm63xx_usb_priv_ehci_cfg_set(void)
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+{
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+ u32 reg;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&usb_priv_reg_lock, flags);
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+
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+ if (BCMCPU_IS_6358()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);
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+ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);
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+
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+ /*
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+ * The magic value comes for the original vendor BSP
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+ * and is needed for USB to work. Datasheet does not
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+ * help, so the magic value is used as-is.
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+ */
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+ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,
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+ USBH_PRIV_TEST_6358_REG);
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+
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+ } else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);
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+ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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+ reg |= USBH_PRIV_SETUP_IOC_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+ }
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+
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+ spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
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+}
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h
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@@ -5,5 +5,7 @@
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void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device);
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void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on);
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+void bcm63xx_usb_priv_ohci_cfg_set(void);
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+void bcm63xx_usb_priv_ehci_cfg_set(void);
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#endif /* BCM63XX_USB_PRIV_H_ */
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