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2ad898e091
Removed upstreamed: generic/backport-6.1/789-STABLE-01-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch [1] generic/backport-6.1/789-STABLE-02-net-dsa-mt7530-fix-link-local-frames-that-ingress-vl.patch [2] generic/backport-6.1/789-STABLE-03-net-dsa-mt7530-fix-handling-of-all-link-local-frames.patch [3] generic/pending-6.1/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch [4] generic/pending-6.1/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch [5] Manual adjusted the following patches: mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=be4512b9ac6fc53e1ca8daccbda84f643215c547 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f1fa919ea59655f73cb3972264e157b8831ba546 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=86c0c154a759f2af9612a04bdf29110f02dce956 4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=6b62bad2da1b338f452a9380639fc9b093d75a25 5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f78807362828ad01db2a9ed005bf79501b620f27 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
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From: Maso Huang <maso.huang@mediatek.com>
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Date: Thu, 7 Sep 2023 10:54:37 +0800
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Subject: [PATCH] arm64: dts: mt7986: add afe
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---
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arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++
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1 files changed, 23 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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@@ -249,6 +249,28 @@
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status = "disabled";
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};
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+ afe: audio-controller@11210000 {
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+ compatible = "mediatek,mt7986-afe";
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+ reg = <0 0x11210000 0 0x9000>;
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+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
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+ <&infracfg CLK_INFRA_AUD_26M_CK>,
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+ <&infracfg CLK_INFRA_AUD_L_CK>,
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+ <&infracfg CLK_INFRA_AUD_AUD_CK>,
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+ <&infracfg CLK_INFRA_AUD_EG2_CK>;
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+ clock-names = "aud_bus_ck",
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+ "aud_26m_ck",
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+ "aud_l_ck",
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+ "aud_aud_ck",
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+ "aud_eg2_ck";
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+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
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+ <&topckgen CLK_TOP_AUD_L_SEL>,
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+ <&topckgen CLK_TOP_A_TUNER_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
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+ <&apmixedsys CLK_APMIXED_APLL2>,
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+ <&topckgen CLK_TOP_APLL2_D4>;
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+ };
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+
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7986-pwm";
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reg = <0 0x10048000 0 0x1000>;
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