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98 lines
3.6 KiB
Diff
98 lines
3.6 KiB
Diff
From ce12bfd48e93b98717a258b8181aed0e19933e1e Mon Sep 17 00:00:00 2001
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From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Date: Thu, 23 May 2013 16:32:52 +0200
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Subject: [PATCH 18/29] pci: mvebu: allow the enumeration of devices beyond
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physical bridges
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Until now, the Marvell PCIe driver was only allowing the enumeration
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of the devices in the secondary bus of the emulated PCI-to-PCI
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bridge. This works fine when a PCIe device is directly connected into
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a PCIe slot of the Marvell board.
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However, when the device connected in the PCIe slot is a physical PCIe
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bridge, beyond which a real PCIe device is connected, it no longer
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worked, as the driver was preventing the Linux PCI core from seeing
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such devices.
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This commit fixes that by ensuring that configuration transactions on
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subordinate busses are properly forwarded on the right PCIe interface.
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Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
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the emulated PCI-to-PCI bridge is properly detected, with the
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following layout:
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-[0000:00]-+-01.0-[01]----00.0
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+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
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| +-05.0-[05]--
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| +-07.0-[06]--
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| \-09.0-[07]----00.0
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\-0a.0-[08]----00.0
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Where the PCIe interface that sits beyond the emulated PCI-to-PCI
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bridge at 09.0 allows to access the secondary bus 02, on which there
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is a PCIe bridge that allows to access the 3 to 7 busses, that are
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subordinates to this bridge. And on one of this bus (bus 7), there is
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one real PCIe device connected.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Acked-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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drivers/pci/host/pci-mvebu.c | 31 ++++++++++++++++++++++++++++---
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1 file changed, 28 insertions(+), 3 deletions(-)
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--- a/drivers/pci/host/pci-mvebu.c
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+++ b/drivers/pci/host/pci-mvebu.c
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@@ -554,7 +554,8 @@ mvebu_pcie_find_port(struct mvebu_pcie *
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if (bus->number == 0 && port->devfn == devfn)
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return port;
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if (bus->number != 0 &&
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- port->bridge.secondary_bus == bus->number)
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+ bus->number >= port->bridge.secondary_bus &&
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+ bus->number <= port->bridge.subordinate_bus)
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return port;
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}
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@@ -578,7 +579,18 @@ static int mvebu_pcie_wr_conf(struct pci
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if (bus->number == 0)
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return mvebu_sw_pci_bridge_write(port, where, size, val);
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- if (!port->haslink || PCI_SLOT(devfn) != 0)
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+ if (!port->haslink)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ /*
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+ * On the secondary bus, we don't want to expose any other
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+ * device than the device physically connected in the PCIe
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+ * slot, visible in slot 0. In slot 1, there's a special
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+ * Marvell device that only makes sense when the Armada is
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+ * used as a PCIe endpoint.
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+ */
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+ if (bus->number == port->bridge.secondary_bus &&
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+ PCI_SLOT(devfn) != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Access the real PCIe interface */
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@@ -609,7 +621,20 @@ static int mvebu_pcie_rd_conf(struct pci
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if (bus->number == 0)
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return mvebu_sw_pci_bridge_read(port, where, size, val);
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- if (!port->haslink || PCI_SLOT(devfn) != 0) {
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+ if (!port->haslink) {
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+ *val = 0xffffffff;
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+ }
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+
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+ /*
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+ * On the secondary bus, we don't want to expose any other
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+ * device than the device physically connected in the PCIe
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+ * slot, visible in slot 0. In slot 1, there's a special
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+ * Marvell device that only makes sense when the Armada is
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+ * used as a PCIe endpoint.
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+ */
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+ if (bus->number == port->bridge.secondary_bus &&
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+ PCI_SLOT(devfn) != 0) {
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*val = 0xffffffff;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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