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https://github.com/openwrt/openwrt.git
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4ed347aaad
Refresh pending patches with make target/linux/refresh. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
107 lines
3.5 KiB
Diff
107 lines
3.5 KiB
Diff
From ace6abaa0f9203083fe4c0a6a74da2d96410b625 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 12:49:33 +0200
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Subject: [PATCH 01/10] net: phy: realtek: rtl8221: allow to configure SERDES
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mode
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The rtl8221 supports multiple SERDES modes:
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- SGMII
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- 2500base-x
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- HiSGMII
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Further it supports rate adaption on SERDES links to allow
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slow ethernet speeds (10/100/1000mbit) to work on 2500base-x/HiSGMII
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links without reducing the SERDES speed.
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When operating without rate adapters the SERDES link will follow the
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ethernet speed.
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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---
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drivers/net/phy/realtek.c | 48 +++++++++++++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/drivers/net/phy/realtek.c
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+++ b/drivers/net/phy/realtek.c
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@@ -53,6 +53,15 @@
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RTL8201F_ISR_LINK)
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#define RTL8201F_IER 0x13
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+#define RTL8221B_MMD_SERDES_CTRL MDIO_MMD_VEND1
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+#define RTL8221B_MMD_PHY_CTRL MDIO_MMD_VEND2
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+#define RTL8221B_SERDES_OPTION 0x697a
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+#define RTL8221B_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
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+#define RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII 0
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+#define RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII 1
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+#define RTL8221B_SERDES_OPTION_MODE_2500BASEX 2
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+#define RTL8221B_SERDES_OPTION_MODE_HISGMII 3
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+
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#define RTL8366RB_POWER_SAVE 0x15
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#define RTL8366RB_POWER_SAVE_ON BIT(12)
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@@ -849,6 +858,48 @@ static irqreturn_t rtl9000a_handle_inter
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return IRQ_HANDLED;
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}
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+static int rtl8221b_config_init(struct phy_device *phydev)
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+{
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+ u16 option_mode;
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+
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+ switch (phydev->interface) {
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ if (!phydev->is_c45) {
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+ option_mode = RTL8221B_SERDES_OPTION_MODE_2500BASEX;
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+ break;
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+ }
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+ fallthrough;
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+ case PHY_INTERFACE_MODE_SGMII:
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+ option_mode = RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII;
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+ break;
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+ default:
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+ return 0;
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+ }
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+
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL,
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+ 0x75f3, 0);
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+
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+ phy_modify_mmd_changed(phydev, RTL8221B_MMD_SERDES_CTRL,
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+ RTL8221B_SERDES_OPTION,
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+ RTL8221B_SERDES_OPTION_MODE_MASK, option_mode);
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+ switch (option_mode) {
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+ case RTL8221B_SERDES_OPTION_MODE_2500BASEX_SGMII:
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+ case RTL8221B_SERDES_OPTION_MODE_2500BASEX:
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd455);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
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+ break;
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+ case RTL8221B_SERDES_OPTION_MODE_HISGMII_SGMII:
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+ case RTL8221B_SERDES_OPTION_MODE_HISGMII:
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6a04, 0x0503);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f10, 0xd433);
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+ phy_write_mmd(phydev, RTL8221B_MMD_SERDES_CTRL, 0x6f11, 0x8020);
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static struct phy_driver realtek_drvs[] = {
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{
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PHY_ID_MATCH_EXACT(0x00008201),
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@@ -1001,6 +1052,7 @@ static struct phy_driver realtek_drvs[]
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PHY_ID_MATCH_EXACT(0x001cc849),
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.name = "RTL8221B-VB-CG 2.5Gbps PHY",
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.get_features = rtl822x_get_features,
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+ .config_init = rtl8221b_config_init,
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.config_aneg = rtl822x_config_aneg,
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.read_status = rtl822x_read_status,
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.suspend = genphy_suspend,
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@@ -1012,6 +1064,7 @@ static struct phy_driver realtek_drvs[]
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.name = "RTL8221B-VM-CG 2.5Gbps PHY",
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.get_features = rtl822x_get_features,
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.config_aneg = rtl822x_config_aneg,
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+ .config_init = rtl8221b_config_init,
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.read_status = rtl822x_read_status,
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.suspend = genphy_suspend,
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.resume = rtlgen_resume,
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