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d9a9caf352
This is preparation for kernel 6.1 support. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
110 lines
3.1 KiB
Diff
110 lines
3.1 KiB
Diff
From: Gabor Juhos <juhosg@openwrt.org>
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Subject: [PATCH] ar71xx: swizzle address for PCI byte/word access on AR71xx
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Closes #11683.
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SVN-Revision: 32639
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---
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.../mips/include/asm/mach-ath79/mangle-port.h | 111 ++++++++++++++++++
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1 file changed, 111 insertions(+)
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create mode 100644 arch/mips/include/asm/mach-ath79/mangle-port.h
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h
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@@ -0,0 +1,37 @@
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+/*
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+ * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h
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+ * Copyright (C) 2003, 2004 Ralf Baechle
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H
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+#define __ASM_MACH_ATH79_MANGLE_PORT_H
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+
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+#ifdef CONFIG_PCI_AR71XX
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+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);
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+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);
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+#else
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+#define ath79_pci_swizzle_b(port) (port)
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+#define ath79_pci_swizzle_w(port) (port)
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+#endif
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+
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+#define __swizzle_addr_b(port) ath79_pci_swizzle_b(port)
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+#define __swizzle_addr_w(port) ath79_pci_swizzle_w(port)
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+#define __swizzle_addr_l(port) (port)
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+#define __swizzle_addr_q(port) (port)
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+
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+# define ioswabb(a, x) (x)
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+# define __mem_ioswabb(a, x) (x)
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+# define ioswabw(a, x) (x)
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+# define __mem_ioswabw(a, x) cpu_to_le16(x)
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+# define ioswabl(a, x) (x)
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+# define __mem_ioswabl(a, x) cpu_to_le32(x)
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+# define ioswabq(a, x) (x)
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+# define __mem_ioswabq(a, x) cpu_to_le64(x)
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+
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+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */
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--- a/arch/mips/pci/pci-ar71xx.c
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+++ b/arch/mips/pci/pci-ar71xx.c
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@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8]
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0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
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};
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+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);
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+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);
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+
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+static inline bool ar71xx_is_pci_addr(unsigned long port)
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+{
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+ unsigned long phys = CPHYSADDR(port);
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+
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+ return (phys >= AR71XX_PCI_MEM_BASE &&
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+ phys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);
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+}
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+
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+static unsigned long ar71xx_pci_swizzle_b(unsigned long port)
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+{
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+ return ar71xx_is_pci_addr(port) ? port ^ 3 : port;
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+}
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+
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+static unsigned long ar71xx_pci_swizzle_w(unsigned long port)
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+{
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+ return ar71xx_is_pci_addr(port) ? port ^ 2 : port;
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+}
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+
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+unsigned long ath79_pci_swizzle_b(unsigned long port)
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+{
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+ if (__ath79_pci_swizzle_b)
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+ return __ath79_pci_swizzle_b(port);
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+
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+ return port;
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+}
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+EXPORT_SYMBOL(ath79_pci_swizzle_b);
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+
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+unsigned long ath79_pci_swizzle_w(unsigned long port)
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+{
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+ if (__ath79_pci_swizzle_w)
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+ return __ath79_pci_swizzle_w(port);
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+
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+ return port;
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+}
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+EXPORT_SYMBOL(ath79_pci_swizzle_w);
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+
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static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
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{
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u32 t;
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@@ -275,6 +314,9 @@ static int ar71xx_pci_probe(struct platf
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register_pci_controller(&apc->pci_ctrl);
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+ __ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;
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+ __ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;
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+
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return 0;
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}
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