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1069514978
Use pending patchset for 2.5GE PHY driver, unifying LED handling accross all MediaTek Ethernet PHYs. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
210 lines
7.1 KiB
Diff
210 lines
7.1 KiB
Diff
From 3c05195fc2c232cd853fc8cebf55310c4605111d Mon Sep 17 00:00:00 2001
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From: "SkyLake.Huang" <skylake.huang@mediatek.com>
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Date: Mon, 1 Jul 2024 18:54:14 +0800
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Subject: [PATCH 10/13] net: phy: mediatek: Extend 1G TX/RX link pulse time
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We observe that some 10G devices' (mostly Marvell's chips inside) 1G
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training time violates specification, which may last 2230ms and affect
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later TX/RX link pulse time. This will invalidate MediaTek series
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gigabit Ethernet PHYs' hardware auto downshift mechanism.
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Without this patch, if someone is trying to use "4-wire" cable to
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connect above devices, MediaTek' gigabit Ethernet PHYs may fail
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to downshift to 100Mbps. (If partner 10G devices' downshift mechanism
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stops at 1G)
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This patch extends our 1G TX/RX link pulse time so that we can still
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link up with those 10G devices.
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Tested device:
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- Netgear GS110EMX's 10G port (Marvell 88X3340P)
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- QNAP QSW-M408-4C
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Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
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---
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drivers/net/phy/mediatek/mtk-ge-soc.c | 2 +
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drivers/net/phy/mediatek/mtk-ge.c | 5 +-
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drivers/net/phy/mediatek/mtk-phy-lib.c | 92 ++++++++++++++++++++++++++
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drivers/net/phy/mediatek/mtk.h | 21 ++++++
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4 files changed, 116 insertions(+), 4 deletions(-)
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--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
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+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
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@@ -1396,6 +1396,7 @@ static struct phy_driver mtk_socphy_driv
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PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
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.name = "MediaTek MT7981 PHY",
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.config_init = mt798x_phy_config_init,
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+ .read_status = mtk_gphy_cl22_read_status,
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.config_intr = genphy_no_config_intr,
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.handle_interrupt = genphy_handle_interrupt_no_ack,
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.probe = mt7981_phy_probe,
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@@ -1413,6 +1414,7 @@ static struct phy_driver mtk_socphy_driv
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PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988),
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.name = "MediaTek MT7988 PHY",
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.config_init = mt798x_phy_config_init,
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+ .read_status = mtk_gphy_cl22_read_status,
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.config_intr = genphy_no_config_intr,
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.handle_interrupt = genphy_handle_interrupt_no_ack,
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.probe = mt7988_phy_probe,
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--- a/drivers/net/phy/mediatek/mtk-ge.c
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+++ b/drivers/net/phy/mediatek/mtk-ge.c
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@@ -9,10 +9,6 @@
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#define MTK_GPHY_ID_MT7530 0x03a29412
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#define MTK_GPHY_ID_MT7531 0x03a29441
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-#define MTK_PHY_PAGE_EXTENDED_1 0x0001
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-#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
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-#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
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-
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#define MTK_PHY_PAGE_EXTENDED_2 0x0002
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#define MTK_PHY_PAGE_EXTENDED_3 0x0003
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#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG11 0x11
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@@ -251,6 +247,7 @@ static struct phy_driver mtk_gephy_drive
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.name = "MediaTek MT7531 PHY",
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.probe = mt7531_phy_probe,
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.config_init = mt7531_phy_config_init,
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+ .read_status = mtk_gphy_cl22_read_status,
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/* Interrupts are handled by the switch, not the PHY
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* itself.
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*/
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--- a/drivers/net/phy/mediatek/mtk-phy-lib.c
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+++ b/drivers/net/phy/mediatek/mtk-phy-lib.c
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@@ -109,6 +109,98 @@ int mtk_phy_write_page(struct phy_device
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}
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EXPORT_SYMBOL_GPL(mtk_phy_write_page);
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+/* This function deals with the case that 1G AN starts but isn't completed. We
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+ * set AN_NEW_LP_CNT_LIMIT with different values time after time to let our
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+ * 1G->100Mbps hardware automatic downshift to fit more partner devices.
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+ */
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+static int extend_an_new_lp_cnt_limit(struct phy_device *phydev)
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+{
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+ int mmd_read_ret;
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+ u32 reg_val;
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+ int timeout;
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+
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+ /* According to table 28-9 & Figure 28-18 in IEEE 802.3,
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+ * link_fail_inhibit_timer of 10/100/1000 Mbps devices ranges from 750
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+ * to "1000ms". Once MTK_PHY_FINAL_SPEED_1000 is set, it means that we
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+ * enter "FLP LINK GOOD CHECK" state, link_fail_inhibit_timer starts and
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+ * this PHY's 1G training starts. If 1G training never starts, we do
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+ * nothing but leave.
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+ */
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+ timeout = read_poll_timeout(mmd_read_ret = phy_read_mmd, reg_val,
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+ (mmd_read_ret < 0) ||
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+ reg_val & MTK_PHY_FINAL_SPEED_1000,
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+ 10000, 1000000, false, phydev,
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+ MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
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+ if (mmd_read_ret < 0)
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+ return mmd_read_ret;
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+
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+ if (!timeout) {
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+ /* Once we found MTK_PHY_FINAL_SPEED_1000 is set, no matter 1G
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+ * AN is completed or not, we'll set AN_NEW_LP_CNT_LIMIT again
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+ * and again.
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+ */
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+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AN_NEW_LP_CNT_LIMIT_MASK,
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+ FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK, 0xf));
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+ mdelay(1500);
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+
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+ timeout = read_poll_timeout(mtk_tr_read, reg_val,
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+ (reg_val & AN_STATE_MASK) !=
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+ (AN_STATE_TX_DISABLE <<
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+ AN_STATE_SHIFT),
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+ 10000, 1000000, false, phydev,
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+ 0x0, 0xf, 0x2);
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+ if (!timeout) {
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+ mdelay(625);
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+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
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+ AN_NEW_LP_CNT_LIMIT_MASK,
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+ FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK,
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+ 0x8));
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+ mdelay(500);
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+ mtk_tr_modify(phydev, 0x0, 0xf, 0x3c,
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+ AN_NEW_LP_CNT_LIMIT_MASK,
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+ FIELD_PREP(AN_NEW_LP_CNT_LIMIT_MASK,
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+ 0xf));
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+ } else {
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+ return -ETIMEDOUT;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+int mtk_gphy_cl22_read_status(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ ret = genphy_read_status(phydev);
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+ if (ret)
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+ return ret;
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+
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+ if (phydev->autoneg == AUTONEG_ENABLE && !phydev->autoneg_complete) {
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+ ret = phy_read_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
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+ MTK_PHY_AUX_CTRL_AND_STATUS);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Once LP_DETECTED is set, it means that"ability_match" in
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+ * IEEE 802.3 Figure 28-18 is set. This happens after we plug in
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+ * cable. Also, LP_DETECTED will be cleared after AN complete.
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+ */
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+ if (!FIELD_GET(MTK_PHY_LP_DETECTED_MASK, ret))
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+ return 0;
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+
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+ ret = phy_read(phydev, MII_CTRL1000);
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+ if (ret & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) {
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+ ret = extend_an_new_lp_cnt_limit(phydev);
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+ if (ret < 0)
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+ return ret;
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+ }
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+ }
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(mtk_gphy_cl22_read_status);
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+
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int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
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unsigned long rules,
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unsigned long supported_triggers)
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--- a/drivers/net/phy/mediatek/mtk.h
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+++ b/drivers/net/phy/mediatek/mtk.h
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@@ -10,8 +10,28 @@
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#define MTK_EXT_PAGE_ACCESS 0x1f
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#define MTK_PHY_PAGE_STANDARD 0x0000
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+#define MTK_PHY_PAGE_EXTENDED_1 0x0001
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+#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14
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+/* suprv_media_select_RefClk */
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+#define MTK_PHY_LP_DETECTED_MASK GENMASK(7, 6)
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+#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4)
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+
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#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
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+/* Registers on Token Ring debug nodes */
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+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x2 */
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+#define AN_STATE_MASK GENMASK(22, 19)
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+#define AN_STATE_SHIFT 19
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+#define AN_STATE_TX_DISABLE 1
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+
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+/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
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+#define AN_NEW_LP_CNT_LIMIT_MASK GENMASK(23, 20)
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+#define AUTO_NP_10XEN BIT(6)
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+
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+/* Registers on MDIO_MMD_VEND1 */
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+#define MTK_PHY_LINK_STATUS_MISC (0xa2)
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+#define MTK_PHY_FINAL_SPEED_1000 BIT(3)
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+
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/* Registers on MDIO_MMD_VEND2 */
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#define MTK_PHY_LED0_ON_CTRL 0x24
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#define MTK_PHY_LED1_ON_CTRL 0x26
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@@ -78,6 +98,7 @@ void __mtk_tr_clr_bits(struct phy_device
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int mtk_phy_read_page(struct phy_device *phydev);
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int mtk_phy_write_page(struct phy_device *phydev, int page);
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+int mtk_gphy_cl22_read_status(struct phy_device *phydev);
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int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
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unsigned long rules,
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unsigned long supported_triggers);
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