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95d3d353f8
Copy patches from patches-6.1 to patches-6.6. No changes. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
58 lines
1.8 KiB
Diff
58 lines
1.8 KiB
Diff
From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
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From: Frank Wunderlich <frank-w@public-files.de>
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Date: Wed, 17 Jan 2024 19:41:11 +0100
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Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
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Infracfg can also operate as reset controller, add support for it.
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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---
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drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
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+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
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@@ -14,6 +14,10 @@
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#include "clk-gate.h"
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#include "clk-mux.h"
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
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+
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+#define MT7988_INFRA_RST0_SET_OFFSET 0x70
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+#define MT7988_INFRA_RST1_SET_OFFSET 0x80
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static DEFINE_SPINLOCK(mt7988_clk_lock);
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@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
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GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
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};
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+static u16 infra_rst_ofs[] = {
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+ MT7988_INFRA_RST0_SET_OFFSET,
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+ MT7988_INFRA_RST1_SET_OFFSET,
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+};
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+
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+static u16 infra_idx_map[] = {
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+ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
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+ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
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+};
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+
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+static struct mtk_clk_rst_desc infra_rst_desc = {
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+ .version = MTK_RST_SET_CLR,
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+ .rst_bank_ofs = infra_rst_ofs,
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+ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
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+ .rst_idx_map = infra_idx_map,
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+ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
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+};
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+
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static const struct mtk_clk_desc infra_desc = {
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.clks = infra_clks,
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.num_clks = ARRAY_SIZE(infra_clks),
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.mux_clks = infra_muxes,
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.num_mux_clks = ARRAY_SIZE(infra_muxes),
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.clk_lock = &mt7988_clk_lock,
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+ .rst_desc = &infra_rst_desc,
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};
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static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
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