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The new cpufreq driver requires different dts bindings. Backport the new driver to kernel 5.4 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
238 lines
6.6 KiB
Diff
238 lines
6.6 KiB
Diff
From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Sat, 22 Feb 2020 18:02:17 +0100
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Subject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings
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Document dedicated cpufreq for Krait CPUs.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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---
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.../bindings/cpufreq/qcom-cpufreq-krait.yaml | 221 ++++++++++++++++++
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1 file changed, 221 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
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@@ -0,0 +1,221 @@
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+# SPDX-License-Identifier: GPL-2.0
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: CPU Frequency scaling driver for Krait SoCs
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+
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+maintainers:
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+ - Ansuel Smith <ansuelsmth@gmail.com>
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+
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+description: |
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+ The krait cpufreq driver is a dedicated frequency scaling driver
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+ based on cpufreq-dt generic driver that scale L2 cache and the
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+ cores. TEST
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+
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+ The L2 cache is scaled based on the max clk across all cores and
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+ the clock is decided based on the opp-level set in the device tree.
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+
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+ Different core freq can be linked to a specific l2 freq and the driver
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+ on frequency change will scale the core and the l2 clk based of the
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+ linked freq.
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+
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+ On Krait SoC is present a bug and on every L2 clk change the driver
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+ needs to set the clk to the idle freq before changing it to the new value.
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+
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+ This requires the qcom cpufreq nvmem driver to parse the different opp
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+ core clk and an additional opp table for the l2 scaling.
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+
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+ If the driver detect broken config (for example missing opp-level) the
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+ cpufreq driver skips the l2 scaling
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+
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+ Referring to this example opp-level can be used to link a range of cpu freq
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+ to a specific l2 freq:
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+ cpu opp freq 384000000 has opp-level 0
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+ l2 opp freq 384000000 has opp-level 0
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+ The driver will scale l2 to 384000000
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+
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+ cpu opp freq 600000000-1000000000 has opp-level 1
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+ l2 opp freq 1000000000 has opp-level 1
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+ The driver will scale l2 to 1000000000
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+
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+allOf:
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+ - $ref: /schemas/cache-controller.yaml#
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+
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+select:
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+ properties:
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+ compatible:
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+ items:
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+ - enum:
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+ - qcom,krait-cache
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+
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+ required:
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+ - compatible
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+
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+properties:
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+ compatible:
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+ items:
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+ - const: qcom,krait-cache
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+ - const: cache
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+
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+ cache-level:
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+ const: 2
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+
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+ clocks:
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+ maxItems: 1
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+
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+ clock-names:
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+ const: l2
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+
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+ l2-supply: true
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+
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+ operating-points-v2: true
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+
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+required:
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+ - compatible
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+ - cache-level
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+ - clocks
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+ - clock-names
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+ - l2-supply
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+ - operating-points-v2
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ cpu0: cpu@0 {
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+ compatible = "qcom,krait";
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+ enable-method = "qcom,kpss-acc-v1";
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+ device_type = "cpu";
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+ reg = <0>;
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+ next-level-cache = <&L2>;
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+ qcom,acc = <&acc0>;
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+ qcom,saw = <&saw0>;
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+ clocks = <&kraitcc 0>, <&kraitcc 4>;
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+ clock-names = "cpu", "l2";
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+ clock-latency = <100000>;
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+ cpu-supply = <&smb208_s2a>;
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+ operating-points-v2 = <&opp_table0>;
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+ voltage-tolerance = <5>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <10>;
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+ #cooling-cells = <2>;
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+ cpu-idle-states = <&CPU_SPC>;
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+ };
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+
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+ /* ... */
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+
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+ };
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+
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+ opp_table0: opp_table0 {
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+ compatible = "operating-points-v2-kryo-cpu";
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+ nvmem-cells = <&speedbin_efuse>;
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+
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+ opp-384000000 {
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+ opp-hz = /bits/ 64 <384000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1000000>;
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+ opp-microvolt-speed0-pvs1-v0 = <925000>;
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+ opp-microvolt-speed0-pvs2-v0 = <875000>;
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+ opp-microvolt-speed0-pvs3-v0 = <800000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1050000>;
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+ opp-microvolt-speed0-pvs1-v0 = <975000>;
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+ opp-microvolt-speed0-pvs2-v0 = <925000>;
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+ opp-microvolt-speed0-pvs3-v0 = <850000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1100000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1025000>;
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+ opp-microvolt-speed0-pvs2-v0 = <995000>;
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+ opp-microvolt-speed0-pvs3-v0 = <900000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1150000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1075000>;
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+ opp-microvolt-speed0-pvs2-v0 = <1025000>;
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+ opp-microvolt-speed0-pvs3-v0 = <950000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1200000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1125000>;
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+ opp-microvolt-speed0-pvs2-v0 = <1075000>;
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+ opp-microvolt-speed0-pvs3-v0 = <1000000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+
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+ opp-1400000000 {
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+ opp-hz = /bits/ 64 <1400000000>;
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+ opp-microvolt-speed0-pvs0-v0 = <1250000>;
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+ opp-microvolt-speed0-pvs1-v0 = <1175000>;
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+ opp-microvolt-speed0-pvs2-v0 = <1125000>;
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+ opp-microvolt-speed0-pvs3-v0 = <1050000>;
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+ opp-supported-hw = <0x1>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+ };
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+
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+ opp_table_l2: opp_table_l2 {
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+ compatible = "operating-points-v2";
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+
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+ opp-384000000 {
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+ opp-hz = /bits/ 64 <384000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <0>;
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+ };
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+ opp-1000000000 {
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+ opp-hz = /bits/ 64 <1000000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <1>;
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+ };
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1150000>;
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+ clock-latency-ns = <100000>;
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+ opp-level = <2>;
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+ };
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+ };
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+
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+ soc {
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+ L2: l2-cache {
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+ compatible = "qcom,krait-cache", "cache";
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+ cache-level = <2>;
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+
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+ clocks = <&kraitcc 4>;
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+ clock-names = "l2";
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+ l2-supply = <&smb208_s1a>;
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+ operating-points-v2 = <&opp_table_l2>;
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+ };
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+ };
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+
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+...
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