mirror of
https://github.com/openwrt/openwrt.git
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72 lines
1.9 KiB
Diff
72 lines
1.9 KiB
Diff
--- linux-2.6.19.2.old/drivers/serial/atmel_serial.c 2007-05-01 13:08:03.000000000 +0200
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+++ linux-2.6.19.2/drivers/serial/atmel_serial.c 2007-05-09 10:21:45.000000000 +0200
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@@ -173,6 +173,34 @@
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at91_set_gpio_value(AT91_PIN_PA21, 0);
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else
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at91_set_gpio_value(AT91_PIN_PA21, 1);
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+
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+ /*
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+ * FDL VersaLink adds GPIOS to provide full modem control on
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+ * USART 0 - Drive DTR and RI pins manually
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+ */
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+ if (mctrl & TIOCM_DTR)
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+ at91_set_gpio_value(AT91_PIN_PB6, 0);
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+ else
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+ at91_set_gpio_value(AT91_PIN_PB6, 1);
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+ if (mctrl & TIOCM_RI)
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+ at91_set_gpio_value(AT91_PIN_PB7, 0);
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+ else
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+ at91_set_gpio_value(AT91_PIN_PB7, 1);
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+ }
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+
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+ /*
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+ * FDL VersaLink adds GPIOS to provide full modem control on
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+ * USART 3 - Drive DTR and RI pins manually
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+ */
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+ if (port->mapbase == AT91RM9200_BASE_US3) {
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+ if (mctrl & TIOCM_DTR)
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+ at91_set_gpio_value(AT91_PIN_PB29, 0);
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+ else
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+ at91_set_gpio_value(AT91_PIN_PB29, 1);
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+ if (mctrl & TIOCM_RI)
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+ at91_set_gpio_value(AT91_PIN_PB2, 0);
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+ else
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+ at91_set_gpio_value(AT91_PIN_PB2, 1);
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}
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}
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#endif
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@@ -210,8 +238,14 @@
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/*
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* The control signals are active low.
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*/
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- if (!(status & ATMEL_US_DCD))
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- ret |= TIOCM_CD;
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+
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+ /*
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+ * Ignore DCD reister for USARTS 0 and 3 as FDL Versalink uses
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+ * GPIO's for these signals
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+ */
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+ if (!(port->mapbase == AT91RM9200_BASE_US0 || port->mapbase == AT91RM9200_BASE_US3))
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+ if (!(status & ATMEL_US_DCD))
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+ ret |= TIOCM_CD;
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if (!(status & ATMEL_US_CTS))
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ret |= TIOCM_CTS;
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if (!(status & ATMEL_US_DSR))
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@@ -219,6 +253,16 @@
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if (!(status & ATMEL_US_RI))
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ret |= TIOCM_RI;
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+ /*
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+ * Read the GPIO's for the FDL VersaLink special case
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+ */
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+ if (port->mapbase == AT91RM9200_BASE_US0)
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+ if (!(at91_get_gpio_value(AT91_PIN_PA19)))
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+ ret |= TIOCM_CD;
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+ if (port->mapbase == AT91RM9200_BASE_US3)
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+ if (!(at91_get_gpio_value(AT91_PIN_PA24)))
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+ ret |= TIOCM_CD;
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+
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return ret;
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}
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