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9ad3ef27b9
Removed upstreamed: backport-5.4/070-v5.5-MIPS-BPF-Restore-MIPS32-cBPF-JIT.patch All other patches automatically rebased. Signed-off-by: John Audia <graysky@archlinux.us>
36 lines
1.1 KiB
Diff
36 lines
1.1 KiB
Diff
From a55a0d71c2b1000c514f30573ced00879754f223 Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Fri, 29 Nov 2019 03:07:14 +0200
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Subject: [PATCH] arm64: dts: fsl: Specify phy-mode for CPU ports
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PHYLINK requires that device tree nodes have a phy-mode or
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phy-connection-type property. The internal Felix ports really are
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connected to the ENETC via 2 back-to-back MACs, so the correct MII type
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is GMII (one of which is overclocked at 2.5Gbaud, but still GMII).
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@@ -813,6 +813,8 @@
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/* internal to-cpu ports */
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port@4 {
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reg = <4>;
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+ phy-mode = "gmii";
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+
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fixed-link {
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speed = <1000>;
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full-duplex;
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@@ -821,6 +823,8 @@
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port@5 {
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reg = <5>;
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ethernet = <&enetc_port3>;
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+ phy-mode = "gmii";
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+
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fixed-link {
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speed = <1000>;
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full-duplex;
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