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e2e2fc3cd0
Add updated patches for 6.6. DMA/cache-handling patches have been reworked / backported from upstream. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
271 lines
7.5 KiB
Diff
271 lines
7.5 KiB
Diff
From aa4febf074cbaad81c981a5c6b55324a6f676fb7 Mon Sep 17 00:00:00 2001
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From: "shengyang.chen" <shengyang.chen@starfivetech.com>
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Date: Tue, 13 Jun 2023 14:22:29 +0800
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Subject: [PATCH 089/116] dt-bindings: display: Add yamls for JH7110 display
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system and hdmi
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StarFive SoCs like the jh7110 use display system based on verisilicon IP, use hdmi
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base on innosilicon IP. Add bindings for them.
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Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com>
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---
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.../display/verisilicon/starfive-hdmi.yaml | 92 +++++++++++++++
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.../display/verisilicon/verisilicon-dc.yaml | 109 ++++++++++++++++++
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.../display/verisilicon/verisilicon-drm.yaml | 41 +++++++
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3 files changed, 242 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/display/verisilicon/starfive-hdmi.yaml
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create mode 100644 Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml
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create mode 100644 Documentation/devicetree/bindings/display/verisilicon/verisilicon-drm.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/display/verisilicon/starfive-hdmi.yaml
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@@ -0,0 +1,92 @@
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+# SPDX-License-Identifier: GPL-2.0
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/display/verisilicon/starfive-hdmi.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive SoC HDMI transmiter
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+
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+description:
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+ The StarFive SoC uses the HDMI signal transmiter based on innosilicon IP
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+ to generate HDMI signal from its input and transmit the signal to the screen.
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+
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+maintainers:
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+ - Keith Zhao <keith.zhao@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,hdmi
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+
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+ reg:
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+ minItems: 1
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+
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+ interrupts:
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+ items:
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+ - description: The HDMI hot plug detection interrupt.
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+
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+ clocks:
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+ items:
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+ - description: System clock of HDMI module.
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+ - description: Mclk clock of HDMI audio.
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+ - description: Bclk clock of HDMI audio.
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+ - description: Pixel clock generated by HDMI module.
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+
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+ clock-names:
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+ items:
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+ - const: sysclk
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+ - const: mclk
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+ - const: bclk
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+ - const: pclk
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+
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+ resets:
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+ items:
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+ - description: Reset for HDMI module.
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+
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+ reset-names:
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+ items:
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+ - const: hdmi_tx
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+
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+ '#sound-dai-cells':
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+ const: 0
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+
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+ port:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description:
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+ Port node with one endpoint connected to a display connector node.
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+
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+required:
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+ - compatible
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+ - reg
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+ - interrupts
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+ - clocks
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+ - clock-names
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+ - resets
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+ - reset-names
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+ - '#sound-dai-cells'
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+ - port
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ hdmi: hdmi@29590000 {
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+ compatible = "starfive,hdmi";
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+ reg = <0x29590000 0x4000>;
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+ interrupts = <99>;
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+ clocks = <&voutcrg 17>,
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+ <&voutcrg 15>,
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+ <&voutcrg 16>,
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+ <&hdmitx0_pixelclk>;
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+ clock-names = "sysclk", "mclk","bclk","pclk";
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+ resets = <&voutcrg 9>;
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+ reset-names = "hdmi_tx";
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+ #sound-dai-cells = <0>;
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+ hdmi_in: port {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ hdmi_input: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&dc_out_dpi0>;
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+ };
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+ };
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+ };
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml
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@@ -0,0 +1,109 @@
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+# SPDX-License-Identifier: GPL-2.0
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/display/verisilicon/verisilicon-dc.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive SoC display controller
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+
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+description:
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+ The StarFive SoC uses the display controller based on Verisilicon IP
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+ to transfer the image data from a video memory
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+ buffer to an external LCD interface.
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+
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+maintainers:
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+ - Keith Zhao <keith.zhao@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: verisilicon,dc8200
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+
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+ reg:
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+ maxItems: 3
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+
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+ interrupts:
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+ items:
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+ - description: The interrupt will be generated when DC finish one frame
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+
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+ clocks:
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+ items:
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+ - description: Clock for display system noc bus.
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+ - description: Pixel clock for display channel 0.
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+ - description: Pixel clock for display channel 1.
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+ - description: Clock for axi interface of display controller.
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+ - description: Core clock for display controller.
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+ - description: Clock for ahb interface of display controller.
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+ - description: External HDMI pixel clock.
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+ - description: Parent clock for pixel clock
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+
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+ clock-names:
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+ items:
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+ - const: clk_vout_noc_disp
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+ - const: clk_vout_pix0
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+ - const: clk_vout_pix1
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+ - const: clk_vout_axi
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+ - const: clk_vout_core
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+ - const: clk_vout_vout_ahb
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+ - const: hdmitx0_pixel
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+ - const: clk_vout_dc8200
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+
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+ resets:
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+ items:
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+ - description: Reset for axi interface of display controller.
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+ - description: Reset for ahb interface of display controller.
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+ - description: Core reset of display controller.
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+
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+ reset-names:
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+ items:
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+ - const: rst_vout_axi
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+ - const: rst_vout_ahb
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+ - const: rst_vout_core
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+
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+ port:
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+ $ref: /schemas/graph.yaml#/properties/port
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+ description:
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+ Port node with one endpoint connected to a hdmi node.
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+
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+required:
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+ - compatible
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+ - reg
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+ - interrupts
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+ - clocks
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+ - clock-names
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+ - resets
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+ - reset-names
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+ - port
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ dc8200: dc8200@29400000 {
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+ compatible = "verisilicon,dc8200";
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+ reg = <0x29400000 0x100>,
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+ <0x29400800 0x2000>,
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+ <0x295B0000 0x90>;
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+ interrupts = <95>;
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+ clocks = <&syscrg 60>,
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+ <&voutcrg 7>,
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+ <&voutcrg 8>,
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+ <&voutcrg 4>,
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+ <&voutcrg 5>,
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+ <&voutcrg 6>,
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+ <&hdmitx0_pixelclk>,
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+ <&voutcrg 1>;
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+ clock-names = "clk_vout_noc_disp", "clk_vout_pix0", "clk_vout_pix1", "clk_vout_axi",
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+ "clk_vout_core", "clk_vout_vout_ahb", "hdmitx0_pixel","clk_vout_dc8200";
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+ resets = <&voutcrg 0>,
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+ <&voutcrg 1>,
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+ <&voutcrg 2>;
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+ reset-names = "rst_vout_axi","rst_vout_ahb","rst_vout_core";
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+ dc_out: port {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ dc_out_dpi0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&hdmi_input>;
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+ };
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+ };
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+ };
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/display/verisilicon/verisilicon-drm.yaml
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@@ -0,0 +1,41 @@
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+# SPDX-License-Identifier: (GPL-2.0-only)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/display/verisilicon/verisilicon-drm.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Verisilicon DRM master device
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+
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+maintainers:
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+ - Keith Zhao <keith.zhao@starfivetech.com>
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+
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+description: |
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+ The Verisilicon DRM master device is a virtual device needed to list all
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+ display controller or other display interface nodes that comprise the
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+ graphics subsystem.
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+
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+properties:
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+ compatible:
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+ const: verisilicon,display-subsystem
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+
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+ ports:
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+ $ref: /schemas/types.yaml#/definitions/phandle-array
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+ items:
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+ maxItems: 1
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+ description: |
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+ Should contain a list of phandles pointing to display interface ports
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+ of display controller devices. Display controller definitions as defined in
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+ Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml
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+
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+required:
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+ - compatible
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+ - ports
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ display-subsystem {
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+ compatible = "verisilicon,display-subsystem";
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+ ports = <&dc_out>;
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+ };
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