mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 22:47:56 +00:00
02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
125 lines
2.8 KiB
Diff
125 lines
2.8 KiB
Diff
From b9eaa80146abb09bcc7e6d8b33fca476453c839c Mon Sep 17 00:00:00 2001
|
|
From: Andy Gross <agross@codeaurora.org>
|
|
Date: Wed, 14 May 2014 22:01:16 -0500
|
|
Subject: [PATCH 137/182] ARM: qcom-ipq8064-ap148: Add SPI related bindings
|
|
|
|
Signed-off-by: Andy Gross <agross@codeaurora.org>
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 42 ++++++++++++++++++++++++++
|
|
arch/arm/boot/dts/qcom-ipq8064.dtsi | 47 ++++++++++++++++++++++++++++++
|
|
2 files changed, 89 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
|
|
@@ -20,6 +20,15 @@
|
|
function = "gsbi4";
|
|
bias-disable;
|
|
};
|
|
+
|
|
+ spi_pins: spi_pins {
|
|
+ mux {
|
|
+ pins = "gpio18", "gpio19", "gpio21";
|
|
+ function = "gsbi5";
|
|
+ drive-strength = <10>;
|
|
+ bias-none;
|
|
+ };
|
|
+ };
|
|
};
|
|
|
|
gsbi@16300000 {
|
|
@@ -38,5 +47,38 @@
|
|
pinctrl-names = "default";
|
|
};
|
|
};
|
|
+
|
|
+ gsbi5: gsbi@1a200000 {
|
|
+ qcom,mode = <GSBI_PROT_SPI>;
|
|
+ status = "ok";
|
|
+
|
|
+ spi4: spi@1a280000 {
|
|
+ status = "ok";
|
|
+ spi-max-frequency = <50000000>;
|
|
+
|
|
+ pinctrl-0 = <&spi_pins>;
|
|
+ pinctrl-names = "default";
|
|
+
|
|
+ cs-gpios = <&qcom_pinmux 20 0>;
|
|
+
|
|
+ flash: m25p80@0 {
|
|
+ compatible = "s25fl256s1";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ spi-max-frequency = <50000000>;
|
|
+ reg = <0>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "rootfs";
|
|
+ reg = <0x0 0x1000000>;
|
|
+ };
|
|
+
|
|
+ partition@1 {
|
|
+ label = "scratch";
|
|
+ reg = <0x1000000 0x1000000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|
|
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
|
|
@@ -187,6 +187,53 @@
|
|
};
|
|
};
|
|
|
|
+ gsbi5: gsbi@1a200000 {
|
|
+ compatible = "qcom,gsbi-v1.0.0";
|
|
+ reg = <0x1a200000 0x100>;
|
|
+ clocks = <&gcc GSBI5_H_CLK>;
|
|
+ clock-names = "iface";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ serial@1a240000 {
|
|
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
+ reg = <0x1a240000 0x1000>,
|
|
+ <0x1a200000 0x1000>;
|
|
+ interrupts = <0 154 0x0>;
|
|
+ clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2c@1a280000 {
|
|
+ compatible = "qcom,i2c-qup-v1.1.1";
|
|
+ reg = <0x1a280000 0x1000>;
|
|
+ interrupts = <0 155 0>;
|
|
+
|
|
+ clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ spi@1a280000 {
|
|
+ compatible = "qcom,spi-qup-v1.1.1";
|
|
+ reg = <0x1a280000 0x1000>;
|
|
+ interrupts = <0 155 0>;
|
|
+
|
|
+ clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
+ clock-names = "core", "iface";
|
|
+ status = "disabled";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
qcom,ssbi@500000 {
|
|
compatible = "qcom,ssbi";
|
|
reg = <0x00500000 0x1000>;
|