mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
e4ce3109f2
The node pinctrl0 is already set up in the SOC DTSI files, but defined again as member of pinctrl in most of the device DTS(I) files. This patch removes this redundancy for the entire ramips target. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
123 lines
1.9 KiB
Plaintext
123 lines
1.9 KiB
Plaintext
/dts-v1/;
|
|
|
|
#include "mt7621.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
compatible = "zbtlink,zbt-wg2626", "mediatek,mt7621-soc";
|
|
model = "Zbtlink ZBT-WG2626";
|
|
|
|
aliases {
|
|
led-boot = &led_status;
|
|
led-failsafe = &led_status;
|
|
led-running = &led_status;
|
|
led-upgrade = &led_status;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,115200";
|
|
};
|
|
|
|
palmbus: palmbus@1E000000 {
|
|
i2c@900 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "reset";
|
|
gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_RESTART>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_status: status {
|
|
label = "zbt-wg2626:green:status";
|
|
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&sdhci {
|
|
status = "okay";
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
m25p80@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <10000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x0 0x30000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@30000 {
|
|
label = "u-boot-env";
|
|
reg = <0x30000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
factory: partition@40000 {
|
|
label = "factory";
|
|
reg = <0x40000 0x10000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@50000 {
|
|
compatible = "denx,uimage";
|
|
label = "firmware";
|
|
reg = <0x50000 0xfb0000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
mt76@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x8000>;
|
|
ieee80211-freq-limit = <5000000 6000000>;
|
|
};
|
|
};
|
|
|
|
&pcie1 {
|
|
mt76@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
mediatek,mtd-eeprom = <&factory 0x0000>;
|
|
ieee80211-freq-limit = <2400000 2500000>;
|
|
};
|
|
};
|
|
|
|
ðernet {
|
|
mtd-mac-address = <&factory 0xe000>;
|
|
};
|
|
|
|
&state_default {
|
|
gpio {
|
|
ralink,group = "wdt", "rgmii2", "jtag", "mdio";
|
|
ralink,function = "gpio";
|
|
};
|
|
};
|