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e4ce3109f2
The node pinctrl0 is already set up in the SOC DTSI files, but defined again as member of pinctrl in most of the device DTS(I) files. This patch removes this redundancy for the entire ramips target. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
112 lines
1.7 KiB
Plaintext
112 lines
1.7 KiB
Plaintext
#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "ubiquiti,edgerouterx", "mediatek,mt7621-soc";
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aliases {
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label-mac-device = ðernet;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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ðernet {
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mtd-mac-address = <&factory 0x22>;
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};
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&nand {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x60000>;
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read-only;
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};
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factory: partition@e0000 {
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label = "factory";
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reg = <0xe0000 0x60000>;
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};
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partition@140000 {
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label = "kernel1";
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reg = <0x140000 0x300000>;
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};
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partition@440000 {
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label = "kernel2";
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reg = <0x440000 0x300000>;
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};
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partition@740000 {
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label = "ubi";
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reg = <0x740000 0xf7c0000>;
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};
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};
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};
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&state_default {
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gpio {
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ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag";
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ralink,function = "gpio";
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};
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};
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&spi0 {
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/*
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* This board has 2Mb spi flash soldered in and visible
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* from manufacturer's firmware.
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* But this SoC shares spi and nand pins,
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* and current driver doesn't handle this sharing well
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*/
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status = "disabled";
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m25p80@1 {
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compatible = "jedec,spi-nor";
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reg = <1>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "spi";
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reg = <0x0 0x200000>;
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read-only;
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};
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};
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};
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};
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&xhci {
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status = "disabled";
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};
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