mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 22:47:56 +00:00
9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
74 lines
2.1 KiB
Diff
74 lines
2.1 KiB
Diff
From 8ea673a8b30b4a32516b8adabb15e2a68ff02ec8 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
|
Date: Tue, 30 Nov 2021 18:29:04 +0100
|
|
Subject: [PATCH] PCI: pci-bridge-emul: Add definitions for missing
|
|
capabilities registers
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
pci-bridge-emul driver already allocates buffer for capabilities up to the
|
|
PCI_EXP_SLTSTA2 register, but does not define bit access behavior for these
|
|
registers. Add these missing definitions.
|
|
|
|
Link: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org
|
|
Signed-off-by: Pali Rohár <pali@kernel.org>
|
|
Signed-off-by: Marek Behún <kabel@kernel.org>
|
|
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
|
---
|
|
drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++
|
|
1 file changed, 43 insertions(+)
|
|
|
|
--- a/drivers/pci/pci-bridge-emul.c
|
|
+++ b/drivers/pci/pci-bridge-emul.c
|
|
@@ -270,6 +270,49 @@ struct pci_bridge_reg_behavior pcie_cap_
|
|
.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
|
|
.w1c = PCI_EXP_RTSTA_PME,
|
|
},
|
|
+
|
|
+ [PCI_EXP_DEVCAP2 / 4] = {
|
|
+ /*
|
|
+ * Device capabilities 2 register has reserved bits [30:27].
|
|
+ * Also bits [26:24] are reserved for non-upstream ports.
|
|
+ */
|
|
+ .ro = BIT(31) | GENMASK(23, 0),
|
|
+ },
|
|
+
|
|
+ [PCI_EXP_DEVCTL2 / 4] = {
|
|
+ /*
|
|
+ * Device control 2 register is RW. Bit 11 is reserved for
|
|
+ * non-upstream ports.
|
|
+ *
|
|
+ * Device status 2 register is reserved.
|
|
+ */
|
|
+ .rw = GENMASK(15, 12) | GENMASK(10, 0),
|
|
+ },
|
|
+
|
|
+ [PCI_EXP_LNKCAP2 / 4] = {
|
|
+ /* Link capabilities 2 register has reserved bits [30:25] and 0. */
|
|
+ .ro = BIT(31) | GENMASK(24, 1),
|
|
+ },
|
|
+
|
|
+ [PCI_EXP_LNKCTL2 / 4] = {
|
|
+ /*
|
|
+ * Link control 2 register is RW.
|
|
+ *
|
|
+ * Link status 2 register has bits 5, 15 W1C;
|
|
+ * bits 10, 11 reserved and others are RO.
|
|
+ */
|
|
+ .rw = GENMASK(15, 0),
|
|
+ .w1c = (BIT(15) | BIT(5)) << 16,
|
|
+ .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
|
|
+ },
|
|
+
|
|
+ [PCI_EXP_SLTCAP2 / 4] = {
|
|
+ /* Slot capabilities 2 register is reserved. */
|
|
+ },
|
|
+
|
|
+ [PCI_EXP_SLTCTL2 / 4] = {
|
|
+ /* Both Slot control 2 and Slot status 2 registers are reserved. */
|
|
+ },
|
|
};
|
|
|
|
/*
|