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99fcc90270
This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
519 lines
16 KiB
Diff
519 lines
16 KiB
Diff
From 5bf84a1a0a282a18bf9dd2d752537525aefc2e05 Mon Sep 17 00:00:00 2001
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From: Max Fierke <max@maxfierke.com>
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Date: Wed, 1 Jun 2022 00:17:48 -0500
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Subject: [PATCH 107/117] drm: panel: Add driver for Clockwork cwd686 panel
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The Clockwork DevTerm (all models) uses a 6.86" IPS display
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of unknown provenance, which uses the Chipone ICNL9707 IC driver.
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The display panel I have has two model numbers: TXW686001 and WTL068601G,
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but cannot find any manufacturer associated with either, so opting for the
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Clockwork model number.
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This driver is based on the GPL-licensed driver released by Clockwork,
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authored by Pinfan Zhu, with some additional cleanup, rotation support,
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and display sleep re-enabling done by me.
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Original driver here for reference: https://github.com/clockworkpi/DevTerm/blob/main/Code/patch/armbian_build_a06/patch/kernel-004-panel.patch
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Display IC datasheet provided here: https://github.com/clockworkpi/DevTerm/blob/main/Schematics/ICNL9707_Datasheet.pdf
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Signed-off-by: Max Fierke <max@maxfierke.com>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/gpu/drm/panel/Kconfig | 12 +
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drivers/gpu/drm/panel/Makefile | 1 +
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.../gpu/drm/panel/panel-clockwork-cwd686.c | 456 ++++++++++++++++++
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3 files changed, 469 insertions(+)
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create mode 100644 drivers/gpu/drm/panel/panel-clockwork-cwd686.c
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--- a/drivers/gpu/drm/panel/Kconfig
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+++ b/drivers/gpu/drm/panel/Kconfig
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@@ -68,6 +68,18 @@ config DRM_PANEL_BOE_TV101WUM_NL6
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Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
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45NA WUXGA PANEL DSI Video Mode panel
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+config DRM_PANEL_CLOCKWORK_CWD686
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+ tristate "Clockwork CWD686 panel"
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+ depends on OF
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+ depends on DRM_MIPI_DSI
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+ depends on BACKLIGHT_CLASS_DEVICE
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+ help
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+ Say Y here if you want to enable support for the Clockwork CWD686
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+ ICNL9707-based panel, e.g. as used within the Clockwork DevTerm.
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+ The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
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+
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+ To compile this driver as a module, choose M here.
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+
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config DRM_PANEL_DSI_CM
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tristate "Generic DSI command mode panels"
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depends on OF
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--- a/drivers/gpu/drm/panel/Makefile
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+++ b/drivers/gpu/drm/panel/Makefile
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@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_N
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obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) += panel-boe-bf060y8m-aj0.o
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obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o
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obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
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+obj-$(CONFIG_DRM_PANEL_CLOCKWORK_CWD686) += panel-clockwork-cwd686.o
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obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
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obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
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obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
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--- /dev/null
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+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
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@@ -0,0 +1,456 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (c) 2021 Clockwork Tech LLC
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+ * Copyright (c) 2021-2022 Max Fierke <max@maxfierke.com>
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+ *
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+ * Based on Pinfan Zhu's work on panel-cwd686.c for ClockworkPi's 5.10 BSP
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+ */
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+
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+#include <drm/drm_modes.h>
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+#include <drm/drm_mipi_dsi.h>
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+#include <drm/drm_panel.h>
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+#include <linux/backlight.h>
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+#include <linux/gpio/consumer.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/delay.h>
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+#include <linux/of_device.h>
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+#include <linux/module.h>
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+#include <video/mipi_display.h>
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+
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+struct cwd686 {
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+ struct device *dev;
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+ struct drm_panel panel;
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+ struct regulator *supply;
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+ struct gpio_desc *enable_gpio;
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+ struct gpio_desc *reset_gpio;
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+ struct backlight_device *backlight;
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+ enum drm_panel_orientation orientation;
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+ bool prepared;
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+ bool enabled;
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+};
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+
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+static const struct drm_display_mode default_mode = {
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+ .clock = 54465,
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+ .hdisplay = 480,
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+ .hsync_start = 480 + 150,
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+ .hsync_end = 480 + 150 + 24,
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+ .htotal = 480 + 150 + 24 + 40,
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+ .vdisplay = 1280,
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+ .vsync_start = 1280 + 12,
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+ .vsync_end = 1280 + 12 + 6,
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+ .vtotal = 1280 + 12 + 6 + 10,
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+};
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+
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+static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
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+{
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+ return container_of(panel, struct cwd686, panel);
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+}
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+
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+#define ICNL9707_DCS(seq...) \
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+({ \
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+ static const u8 d[] = { seq }; \
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+ mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
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+})
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+
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+#define ICNL9707_CMD_CGOUTL 0xB3
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+#define ICNL9707_CMD_CGOUTR 0xB4
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+#define ICNL9707_P_CGOUT_VGL 0x00
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+#define ICNL9707_P_CGOUT_VGH 0x01
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+#define ICNL9707_P_CGOUT_HZ 0x02
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+#define ICNL9707_P_CGOUT_GND 0x03
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+#define ICNL9707_P_CGOUT_GSP1 0x04
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+#define ICNL9707_P_CGOUT_GSP2 0x05
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+#define ICNL9707_P_CGOUT_GSP3 0x06
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+#define ICNL9707_P_CGOUT_GSP4 0x07
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+#define ICNL9707_P_CGOUT_GSP5 0x08
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+#define ICNL9707_P_CGOUT_GSP6 0x09
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+#define ICNL9707_P_CGOUT_GSP7 0x0A
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+#define ICNL9707_P_CGOUT_GSP8 0x0B
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+#define ICNL9707_P_CGOUT_GCK1 0x0C
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+#define ICNL9707_P_CGOUT_GCK2 0x0D
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+#define ICNL9707_P_CGOUT_GCK3 0x0E
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+#define ICNL9707_P_CGOUT_GCK4 0x0F
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+#define ICNL9707_P_CGOUT_GCK5 0x10
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+#define ICNL9707_P_CGOUT_GCK6 0x11
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+#define ICNL9707_P_CGOUT_GCK7 0x12
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+#define ICNL9707_P_CGOUT_GCK8 0x13
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+#define ICNL9707_P_CGOUT_GCK9 0x14
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+#define ICNL9707_P_CGOUT_GCK10 0x15
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+#define ICNL9707_P_CGOUT_GCK11 0x16
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+#define ICNL9707_P_CGOUT_GCK12 0x17
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+#define ICNL9707_P_CGOUT_GCK13 0x18
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+#define ICNL9707_P_CGOUT_GCK14 0x19
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+#define ICNL9707_P_CGOUT_GCK15 0x1A
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+#define ICNL9707_P_CGOUT_GCK16 0x1B
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+#define ICNL9707_P_CGOUT_DIR 0x1C
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+#define ICNL9707_P_CGOUT_DIRB 0x1D
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+#define ICNL9707_P_CGOUT_ECLK_AC 0x1E
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+#define ICNL9707_P_CGOUT_ECLK_ACB 0x1F
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+#define ICNL9707_P_CGOUT_ECLK_AC2 0x20
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+#define ICNL9707_P_CGOUT_ECLK_AC2B 0x21
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+#define ICNL9707_P_CGOUT_GCH 0x22
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+#define ICNL9707_P_CGOUT_GCL 0x23
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+#define ICNL9707_P_CGOUT_XDON 0x24
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+#define ICNL9707_P_CGOUT_XDONB 0x25
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+
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+#define ICNL9707_MADCTL_ML 0x10
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+#define ICNL9707_MADCTL_RGB 0x00
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+#define ICNL9707_MADCTL_BGR 0x08
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+#define ICNL9707_MADCTL_MH 0x04
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+
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+#define ICNL9707_CMD_PWRCON_VCOM 0xB6
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+#define ICNL9707_P_PWRCON_VCOM_0495V 0x0D
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+
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+#define ICNL9707_CMD_PWRCON_SEQ 0xB7
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+#define ICNL9707_CMD_PWRCON_CLK 0xB8
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+#define ICNL9707_CMD_PWRCON_BTA 0xB9
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+#define ICNL9707_CMD_PWRCON_MODE 0xBA
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+#define ICNL9707_CMD_PWRCON_REG 0xBD
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+
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+#define ICNL9707_CMD_TCON 0xC1
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+#define ICNL9707_CMD_TCON2 0xC2
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+#define ICNL9707_CMD_TCON3 0xC3
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+#define ICNL9707_CMD_SRC_TIM 0xC6
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+#define ICNL9707_CMD_SRCCON 0xC7
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+#define ICNL9707_CMD_SET_GAMMA 0xC8
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+
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+#define ICNL9707_CMD_ETC 0xD0
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+
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+#define ICNL9707_CMD_PASSWORD1 0xF0
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+#define ICNL9707_P_PASSWORD1_DEFAULT 0xA5
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+#define ICNL9707_P_PASSWORD1_ENABLE_LVL2 0x5A
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+
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+#define ICNL9707_CMD_PASSWORD2 0xF1
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+#define ICNL9707_P_PASSWORD2_DEFAULT 0x5A
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+#define ICNL9707_P_PASSWORD2_ENABLE_LVL2 0xA5
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+
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+static int cwd686_init_sequence(struct cwd686 *ctx)
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+{
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+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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+ int err;
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+
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+ /* Enable access to Level 2 registers */
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+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
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+ ICNL9707_P_PASSWORD1_ENABLE_LVL2,
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+ ICNL9707_P_PASSWORD1_ENABLE_LVL2);
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+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
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+ ICNL9707_P_PASSWORD2_ENABLE_LVL2,
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+ ICNL9707_P_PASSWORD2_ENABLE_LVL2);
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+
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+ /* Set PWRCON_VCOM (-0.495V, -0.495V) */
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+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
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+ ICNL9707_P_PWRCON_VCOM_0495V,
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+ ICNL9707_P_PWRCON_VCOM_0495V);
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+
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+ /* Map ASG output signals */
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+ ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
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+ ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
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+ ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
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+ ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
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+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
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+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
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+ ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
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+ ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
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+ ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
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+ ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
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+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
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+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
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+ ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
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+
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+ /* Undocumented commands provided by the vendor */
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+ ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
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+ ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
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+ ICNL9707_DCS(0xB2, 0x73);
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+
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+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
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+ 0x4E, 0x0E, 0x50, 0x50, 0x26,
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+ 0x1D, 0x00, 0x14, 0x42, 0x03);
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+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
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+ 0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
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+ 0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
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+ 0x00, 0x00, 0x02, 0xFF, 0x3C);
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+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
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+
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+ /* Disable abnormal power-off flag */
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+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
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+
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+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
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+
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+ /* Set VBP, VFP, VSW, HBP, HFP, HSW */
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+ ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
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+
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+ /* Set resolution */
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+ ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
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+
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+ /* Set frame blanking */
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+ ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
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+
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+ ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
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+
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+ /* Another undocumented command */
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+ ICNL9707_DCS(0xC5, 0x00);
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+
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+ ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
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+
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+ /* Another set of undocumented commands */
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+ ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
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+ ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
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+
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+ /* Set Gamma to 2.2 */
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+ ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
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+ 0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
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+ 0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
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+ 0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
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+ 0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
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+ 0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
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+ 0x3B, 0x2A, 0x06);
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+
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+ ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
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+
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+ /* Another undocumented command */
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+ ICNL9707_DCS(0xF4, 0x08, 0x77);
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+
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+ ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
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+ ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
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+
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+ /* Enable tearing mode at VBLANK */
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+ err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
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+ if (err) {
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+ dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
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+ return err;
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+ }
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+
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+ /* Disable access to Level 2 registers */
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+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
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+ ICNL9707_P_PASSWORD2_DEFAULT,
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+ ICNL9707_P_PASSWORD2_DEFAULT);
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+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
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+ ICNL9707_P_PASSWORD1_DEFAULT,
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+ ICNL9707_P_PASSWORD1_DEFAULT);
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+
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+ return 0;
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+}
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+
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+static int cwd686_disable(struct drm_panel *panel)
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+{
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+ struct cwd686 *ctx = panel_to_cwd686(panel);
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+
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+ if (!ctx->enabled)
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+ return 0;
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+
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+ backlight_disable(ctx->backlight);
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+
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+ ctx->enabled = false;
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+
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+ return 0;
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+}
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+
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+static int cwd686_unprepare(struct drm_panel *panel)
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+{
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+ struct cwd686 *ctx = panel_to_cwd686(panel);
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+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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+ int err;
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+
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+ if (!ctx->prepared)
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+ return 0;
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+
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+ err = mipi_dsi_dcs_set_display_off(dsi);
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+ if (err) {
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+ dev_err(ctx->dev, "failed to turn display off (%d)\n", err);
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+ return err;
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+ }
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+
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+ err = mipi_dsi_dcs_enter_sleep_mode(dsi);
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+ if (err) {
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+ dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", err);
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+ return err;
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+ }
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+
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+ msleep(120);
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+
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+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
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+
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+ ctx->prepared = false;
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+
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+ return 0;
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+}
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+
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+static int cwd686_prepare(struct drm_panel *panel)
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+{
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+ struct cwd686 *ctx = panel_to_cwd686(panel);
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+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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+ int err;
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+
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+ if (ctx->prepared)
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+ return 0;
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+
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+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
|
|
+ /* T2 */
|
|
+ msleep(10);
|
|
+
|
|
+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
|
|
+ /* T3 */
|
|
+ msleep(20);
|
|
+
|
|
+ /* Exit sleep mode and power on */
|
|
+
|
|
+ err = cwd686_init_sequence(ctx);
|
|
+ if (err) {
|
|
+ dev_err(ctx->dev, "failed to initialize display (%d)\n", err);
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ err = mipi_dsi_dcs_exit_sleep_mode(dsi);
|
|
+ if (err) {
|
|
+ dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", err);
|
|
+ return err;
|
|
+ }
|
|
+ /* T6 */
|
|
+ msleep(120);
|
|
+
|
|
+ err = mipi_dsi_dcs_set_display_on(dsi);
|
|
+ if (err) {
|
|
+ dev_err(ctx->dev, "failed to turn display on (%d)\n", err);
|
|
+ return err;
|
|
+ }
|
|
+ msleep(20);
|
|
+
|
|
+ ctx->prepared = true;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int cwd686_enable(struct drm_panel *panel)
|
|
+{
|
|
+ struct cwd686 *ctx = panel_to_cwd686(panel);
|
|
+
|
|
+ if (ctx->enabled)
|
|
+ return 0;
|
|
+
|
|
+ backlight_enable(ctx->backlight);
|
|
+
|
|
+ ctx->enabled = true;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
|
|
+{
|
|
+ struct cwd686 *ctx = panel_to_cwd686(panel);
|
|
+ struct drm_display_mode *mode;
|
|
+
|
|
+ mode = drm_mode_duplicate(connector->dev, &default_mode);
|
|
+ if (!mode) {
|
|
+ dev_err(panel->dev, "bad mode or failed to add mode\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ drm_mode_set_name(mode);
|
|
+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
|
|
+
|
|
+ connector->display_info.width_mm = mode->width_mm;
|
|
+ connector->display_info.height_mm = mode->height_mm;
|
|
+
|
|
+ /* set up connector's "panel orientation" property */
|
|
+ drm_connector_set_panel_orientation(connector, ctx->orientation);
|
|
+
|
|
+ drm_mode_probed_add(connector, mode);
|
|
+
|
|
+ return 1; /* Number of modes */
|
|
+}
|
|
+
|
|
+static const struct drm_panel_funcs cwd686_drm_funcs = {
|
|
+ .disable = cwd686_disable,
|
|
+ .unprepare = cwd686_unprepare,
|
|
+ .prepare = cwd686_prepare,
|
|
+ .enable = cwd686_enable,
|
|
+ .get_modes = cwd686_get_modes,
|
|
+};
|
|
+
|
|
+static int cwd686_probe(struct mipi_dsi_device *dsi)
|
|
+{
|
|
+ struct device *dev = &dsi->dev;
|
|
+ struct cwd686 *ctx;
|
|
+ int err;
|
|
+
|
|
+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
|
|
+ if (!ctx)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ mipi_dsi_set_drvdata(dsi, ctx);
|
|
+ ctx->dev = dev;
|
|
+
|
|
+ dsi->lanes = 4;
|
|
+ dsi->format = MIPI_DSI_FMT_RGB888;
|
|
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
|
|
+ MIPI_DSI_MODE_VIDEO_BURST |
|
|
+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
|
|
+
|
|
+ ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
|
|
+ if (IS_ERR(ctx->reset_gpio)) {
|
|
+ err = PTR_ERR(ctx->reset_gpio);
|
|
+ if (err != -EPROBE_DEFER)
|
|
+ dev_err(dev, "failed to request GPIO (%d)\n", err);
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ ctx->backlight = devm_of_find_backlight(dev);
|
|
+ if (IS_ERR(ctx->backlight))
|
|
+ return PTR_ERR(ctx->backlight);
|
|
+
|
|
+ err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
|
|
+ if (err) {
|
|
+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
|
|
+
|
|
+ drm_panel_add(&ctx->panel);
|
|
+
|
|
+ err = mipi_dsi_attach(dsi);
|
|
+ if (err < 0) {
|
|
+ dev_err(dev, "mipi_dsi_attach() failed: %d\n", err);
|
|
+ drm_panel_remove(&ctx->panel);
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void cwd686_remove(struct mipi_dsi_device *dsi)
|
|
+{
|
|
+ struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
|
|
+
|
|
+ mipi_dsi_detach(dsi);
|
|
+ drm_panel_remove(&ctx->panel);
|
|
+}
|
|
+
|
|
+static const struct of_device_id cwd686_of_match[] = {
|
|
+ { .compatible = "clockwork,cwd686" },
|
|
+ { /* sentinel */ }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, cwd686_of_match);
|
|
+
|
|
+static struct mipi_dsi_driver cwd686_driver = {
|
|
+ .probe = cwd686_probe,
|
|
+ .remove = cwd686_remove,
|
|
+ .driver = {
|
|
+ .name = "panel-clockwork-cwd686",
|
|
+ .of_match_table = cwd686_of_match,
|
|
+ },
|
|
+};
|
|
+module_mipi_dsi_driver(cwd686_driver);
|
|
+
|
|
+MODULE_AUTHOR("Pinfan Zhu <zhu@clockworkpi.com>");
|
|
+MODULE_AUTHOR("Max Fierke <max@maxfierke.com>");
|
|
+MODULE_DESCRIPTION("ClockworkPi CWD686 panel driver");
|
|
+MODULE_LICENSE("GPL");
|