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99fcc90270
This is an automatically generated commit. When doing `git bisect`, consider `git bisect --skip`. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
155 lines
3.6 KiB
Diff
155 lines
3.6 KiB
Diff
From aaabd3cf8c041b5122ca252f51fa616833e18749 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Thu, 11 Aug 2022 00:54:01 -0500
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Subject: [PATCH 078/117] riscv: dts: allwinner: Add SPI support
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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.../dts/allwinner/sun20i-d1-lichee-rv.dts | 6 +++
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.../boot/dts/allwinner/sun20i-d1-nezha.dts | 44 ++++++++++++++++
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arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 51 +++++++++++++++++++
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3 files changed, 101 insertions(+)
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--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
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+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
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@@ -65,6 +65,12 @@
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status = "okay";
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};
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+&spi0 {
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+ pinctrl-0 = <&spi0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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&uart0 {
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pinctrl-0 = <&uart0_pb8_pins>;
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pinctrl-names = "default";
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--- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
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+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
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@@ -19,6 +19,7 @@
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ethernet1 = &xr829;
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mmc0 = &mmc0;
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serial0 = &uart0;
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+ spi0 = &spi0;
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};
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chosen {
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@@ -157,6 +158,49 @@
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pinctrl-names = "default";
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status = "okay";
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};
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+
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+&spi0 {
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+ pinctrl-0 = <&spi0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "boot0";
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+ reg = <0x00000000 0x00100000>;
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+ };
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+
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+ partition@100000 {
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+ label = "uboot";
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+ reg = <0x00100000 0x00300000>;
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+ };
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+
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+ partition@400000 {
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+ label = "secure_storage";
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+ reg = <0x00400000 0x00100000>;
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+ };
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+
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+ partition@500000 {
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+ label = "sys";
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+ reg = <0x00500000 0x0fb00000>;
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+ };
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+ };
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+ };
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+};
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+
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+&spi1 {
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+ pinctrl-0 = <&spi1_pd_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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&uart0 {
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pinctrl-0 = <&uart0_pb8_pins>;
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--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
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+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
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@@ -179,6 +179,24 @@
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};
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/omit-if-no-ref/
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+ spi0_pins: spi0-pins {
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+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
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+ function = "spi0";
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+ };
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+
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+ /omit-if-no-ref/
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+ spi1_pb_pins: spi1-pb-pins {
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+ pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12";
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+ function = "spi1";
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+ };
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+
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+ /omit-if-no-ref/
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+ spi1_pd_pins: spi1-pd-pins {
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+ pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
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+ function = "spi1";
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+ };
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+
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+ /omit-if-no-ref/
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uart0_pb8_pins: uart0-pb8-pins {
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pins = "PB8", "PB9";
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function = "uart0";
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@@ -631,6 +649,39 @@
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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+ };
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+
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+ spi0: spi@4025000 {
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+ compatible = "allwinner,sun20i-d1-spi",
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+ "allwinner,sun50i-r329-spi";
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+ reg = <0x4025000 0x1000>;
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+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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+ clock-names = "ahb", "mod";
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+ resets = <&ccu RST_BUS_SPI0>;
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+ dmas = <&dma 22>, <&dma 22>;
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+ dma-names = "rx", "tx";
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+ num-cs = <1>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@4026000 {
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+ compatible = "allwinner,sun20i-d1-spi-dbi",
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+ "allwinner,sun50i-r329-spi-dbi",
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+ "allwinner,sun50i-r329-spi";
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+ reg = <0x4026000 0x1000>;
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+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
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+ clock-names = "ahb", "mod";
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+ resets = <&ccu RST_BUS_SPI1>;
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+ dmas = <&dma 23>, <&dma 23>;
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+ dma-names = "rx", "tx";
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+ num-cs = <1>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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};
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usb_otg: usb@4100000 {
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