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f2e1e156c0
This adds support for eBPF JIT for 32 bit targets and significantly improves correctness. Signed-off-by: Felix Fietkau <nbd@nbd.name>
66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
From: Johan Almbladh <johan.almbladh@anyfinetworks.com>
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Date: Tue, 5 Oct 2021 18:54:02 +0200
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Subject: [PATCH] MIPS: uasm: Enable muhu opcode for MIPS R6
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Enable the 'muhu' instruction, complementing the existing 'mulu', needed
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to implement a MIPS32 BPF JIT.
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Also fix a typo in the existing definition of 'dmulu'.
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Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
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This patch is a dependency for my 32-bit MIPS eBPF JIT.
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Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
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---
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--- a/arch/mips/include/asm/uasm.h
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+++ b/arch/mips/include/asm/uasm.h
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@@ -145,6 +145,7 @@ Ip_u1(_mtlo);
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Ip_u3u1u2(_mul);
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Ip_u1u2(_multu);
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Ip_u3u1u2(_mulu);
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+Ip_u3u1u2(_muhu);
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Ip_u3u1u2(_nor);
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Ip_u3u1u2(_or);
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Ip_u2u1u3(_ori);
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--- a/arch/mips/mm/uasm-mips.c
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+++ b/arch/mips/mm/uasm-mips.c
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@@ -90,7 +90,7 @@ static const struct insn insn_table[insn
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RS | RT | RD},
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[insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
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[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
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- [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),
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+ [insn_dmulu] = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),
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RS | RT | RD},
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[insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
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[insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
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@@ -150,6 +150,8 @@ static const struct insn insn_table[insn
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[insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
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[insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
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RS | RT | RD},
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+ [insn_muhu] = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),
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+ RS | RT | RD},
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#ifndef CONFIG_CPU_MIPSR6
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[insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
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#else
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--- a/arch/mips/mm/uasm.c
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+++ b/arch/mips/mm/uasm.c
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@@ -59,7 +59,7 @@ enum opcode {
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insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
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insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
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insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
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- insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
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+ insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,
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insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
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insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
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insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
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@@ -344,6 +344,7 @@ I_u1(_mtlo)
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I_u3u1u2(_mul)
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I_u1u2(_multu)
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I_u3u1u2(_mulu)
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+I_u3u1u2(_muhu)
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I_u3u1u2(_nor)
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I_u3u1u2(_or)
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I_u2u1u3(_ori)
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