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92 lines
2.1 KiB
Diff
92 lines
2.1 KiB
Diff
From 3f0a06b0368d25608841843e9d65a7289ad9f14a Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 20 Jan 2013 22:01:29 +0100
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Subject: [PATCH 05/14] MIPS: ralink: adds clkdev code
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These SoCs have a limited number of fixed rate clocks. Add support for the
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clk and clkdev api.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4894/
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---
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arch/mips/ralink/clk.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 72 insertions(+)
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create mode 100644 arch/mips/ralink/clk.c
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--- /dev/null
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+++ b/arch/mips/ralink/clk.c
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@@ -0,0 +1,72 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/clkdev.h>
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+#include <linux/clk.h>
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+
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+#include <asm/time.h>
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+
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+#include "common.h"
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+
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+struct clk {
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+ struct clk_lookup cl;
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+ unsigned long rate;
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+};
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+
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+void ralink_clk_add(const char *dev, unsigned long rate)
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+{
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+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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+
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+ if (!clk)
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+ panic("failed to add clock\n");
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+
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+ clk->cl.dev_id = dev;
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+ clk->cl.clk = clk;
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+
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+ clk->rate = rate;
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+
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+ clkdev_add(&clk->cl);
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+}
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+
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+/*
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+ * Linux clock API
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+ */
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+int clk_enable(struct clk *clk)
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+{
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(clk_enable);
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+
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+void clk_disable(struct clk *clk)
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+{
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+}
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+EXPORT_SYMBOL_GPL(clk_disable);
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+
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+unsigned long clk_get_rate(struct clk *clk)
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+{
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+ return clk->rate;
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+}
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+EXPORT_SYMBOL_GPL(clk_get_rate);
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+
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+void __init plat_time_init(void)
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+{
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+ struct clk *clk;
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+
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+ ralink_of_remap();
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+
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+ ralink_clk_init();
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+ clk = clk_get_sys("cpu", NULL);
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+ if (IS_ERR(clk))
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+ panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
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+ pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
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+ mips_hpt_frequency = clk_get_rate(clk) / 2;
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+ clk_put(clk);
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+}
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