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98684d99b2
Signed-off-by: Marko Ratkaj <marko.ratkaj@sartura.hr> [added sfp related patches from Russell King] Signed-off-by: Marek Behún <marek.behun@nic.cz> [rebase; rework patches; separate and cleanup kernel configs; add espessobin dts; adjust venom dts] Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
44 lines
1.4 KiB
Diff
44 lines
1.4 KiB
Diff
From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
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From: Tomasz Maciej Nowak <tmn505@gmail.com>
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Date: Thu, 14 Jun 2018 14:24:40 +0200
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Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
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Use DT of_pci_get_max_link_speed() facility to allow specifying link
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capability. If none or unspecified value is given it falls back to gen2,
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which is default for Armada 3700 SoC.
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Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
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---
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drivers/pci/controller/pci-aardvark.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc
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static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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{
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+ struct device *dev = &pcie->pdev->dev;
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+ struct device_node *node = dev->of_node;
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u32 reg;
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/* Set to Direct mode */
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@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad
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PCIE_CORE_CTRL2_TD_ENABLE;
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advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
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- /* Set GEN2 */
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+ /* Set GEN */
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reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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reg &= ~PCIE_GEN_SEL_MSK;
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- reg |= SPEED_GEN_2;
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+ if (of_pci_get_max_link_speed(node) == 1)
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+ reg |= SPEED_GEN_1;
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+ else if (of_pci_get_max_link_speed(node) == 3)
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+ reg |= SPEED_GEN_3;
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+ else
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+ reg |= SPEED_GEN_2;
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advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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/* Set lane X1 */
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