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e4db63fd64
The nand subtarget is not working yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 33983
94 lines
2.6 KiB
Diff
94 lines
2.6 KiB
Diff
From e4ba5e2bffd1f373f57dd692233aa6b7b46ae76c Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 24 Jun 2012 13:47:35 +0200
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Subject: [PATCH 23/34] MIPS: ath79: add USB controller registration code for the QCA955X SoCs
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/dev-usb.c | 46 ++++++++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 4 ++
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2 files changed, 50 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/dev-usb.c
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+++ b/arch/mips/ath79/dev-usb.c
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@@ -75,6 +75,8 @@ static void __init ath79_usb_init_resour
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unsigned long size,
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int irq)
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{
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+ memset(res, 0, sizeof(res));
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+
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res[0].flags = IORESOURCE_MEM;
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res[0].start = base;
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res[0].end = base + size - 1;
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@@ -219,6 +221,48 @@ static void __init ar934x_usb_setup(void
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platform_device_register(&ath79_ehci_device);
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}
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+static void __init qca955x_usb_setup(void)
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+{
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+ struct platform_device *pdev;
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+
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+ ath79_usb_init_resource(ath79_ehci_resources,
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+ QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
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+ ATH79_IP3_IRQ(0));
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+
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+ pdev = platform_device_register_resndata(NULL, "ehci-platform", 0,
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+ ath79_ehci_resources,
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+ ARRAY_SIZE(ath79_ehci_resources),
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+ &ath79_ehci_pdata_v2,
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+ sizeof(ath79_ehci_pdata_v2));
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+ if (IS_ERR(pdev)) {
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+ pr_err("Unable to register USB %d device, err=%d\n", 0,
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+ (int) PTR_ERR(pdev));
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+ return;
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+ }
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+
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+ pdev->dev.dma_mask = &ath79_ehci_dmamask;
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+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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+
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+ ath79_usb_init_resource(ath79_ehci_resources,
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+ QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
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+ ATH79_IP3_IRQ(1));
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+
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+ pdev = platform_device_register_resndata(NULL, "ehci-platform", 1,
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+ ath79_ehci_resources,
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+ ARRAY_SIZE(ath79_ehci_resources),
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+ &ath79_ehci_pdata_v2,
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+ sizeof(ath79_ehci_pdata_v2));
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+
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+ if (IS_ERR(pdev)) {
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+ pr_err("Unable to register USB %d device, err=%d\n", 1,
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+ (int) PTR_ERR(pdev));
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+ return;
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+ }
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+
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+ pdev->dev.dma_mask = &ath79_ehci_dmamask;
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+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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+}
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+
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void __init ath79_register_usb(void)
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{
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if (soc_is_ar71xx())
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@@ -233,6 +277,8 @@ void __init ath79_register_usb(void)
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ar933x_usb_setup();
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else if (soc_is_ar934x())
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ar934x_usb_setup();
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+ else if (soc_is_qca955x())
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+ qca955x_usb_setup();
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else
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BUG();
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -94,6 +94,10 @@
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#define AR934X_EHCI_BASE 0x1b000000
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#define AR934X_EHCI_SIZE 0x200
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+#define QCA955X_EHCI0_BASE 0x1b000000
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+#define QCA955X_EHCI1_BASE 0x1b400000
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+#define QCA955X_EHCI_SIZE 0x200
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+
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/*
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* DDR_CTRL block
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*/
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