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b14e529dd7
Specifications:
- FCC ID: KA2IR615E3
- SoC: MIPS32 24K 400 MHz Atheros AR7240
- RAM: 32 MiB DDR SDRAM ESMT M13S2561616A-5T
- Flash: 4 MiB NOR SPI Macronix MX25L3208E
- Wireless: AR9287 2.4 GHz 802.11n 2T2R, 2x RP-SMA connectors
- Ethernet: 5x 100BASE-TX Fast Ethernet
- LEDs: 9x GPIO, 1x ath9k
- Buttons: 2x tactile switches
- UART: 3.3 V, 115200 8n1
- USB: simple hardware modification required, 1x USB 1.1 Full Speed
Partitioning notes:
Vendor firmware (based on CameoAP99) defines two additional partitions:
"mac" @0x3b0000, size 0x10000 and "lp" @0x3c0000, size 0x30000.
The "mac" partition stores LAN MAC address and hardware board name.
However, the vendor firmware uses addresses from "nvram" partition, and
the board name is used only for informational purposes in the Web
interface (included in the pages' header), not affecting the firmware
image check.
The "lp" partition is supposed to contain a "language pack" (which can
be used to add an additional language support to the Web interface) and
is flashed separately, using the vendor firmware upgrade page.
Since these partitions are absolutely useless for OpenWrt and
overwriting them doesn't prevent downgrading to obsolete vendor
firmware, this patch appends the valueable space to "firmware".
Installation instructions:
- Upgrade from OpenWrt ar71xx with "sysupgrade -f -n"
or
- Upload as a firmware update via the vendor Web-interface
or
- Connect UART and use "loady" to upload and run OpenWrt initramfs
image, then sysupgrade from it (TFTP client doesn't work)
or
- Before powering up hold "reset" button and keep it pressed for about
15 seconds after, then access fail safe Web server on 192.168.0.1 (the
old uIP TCP/IP protocol stack is not compatible with modern Linux, the
kernel, so you'll need to use some other OS to do this). Can be
performed without a Web-browser too:
curl http://192.168.0.1/cgi/index \
-F Send=@openwrt-ath79-tiny-dlink_dir-615-e4-squashfs-factory.bin
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
171 lines
2.7 KiB
Plaintext
171 lines
2.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "ar7240.dtsi"
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/ {
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model = "D-Link DIR-615 E4";
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compatible = "dlink,dir-615-e4", "qca,ar7240";
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aliases {
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led-boot = &led_power_amber;
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led-failsafe = &led_power_amber;
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led-running = &led_power_green;
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led-upgrade = &led_power_amber;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&switch_led_pins>;
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led_power_green: power_green {
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label = "d-link:green:power";
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gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
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};
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led_power_amber: power_amber {
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label = "d-link:amber:power";
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gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
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};
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wps {
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label = "d-link:blue:wps";
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gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
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};
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lan1 {
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label = "d-link:green:lan1";
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
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};
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lan2 {
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label = "d-link:green:lan2";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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};
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lan3 {
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label = "d-link:green:lan3";
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
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};
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lan4 {
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label = "d-link:green:lan4";
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gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
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};
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wan_amber {
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label = "d-link:amber:wan";
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gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
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};
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wan_green {
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label = "d-link:green:wan";
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gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
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};
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};
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ath9k-leds {
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compatible = "gpio-leds";
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wlan {
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label = "d-link:green:wlan";
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gpios = <&ath9k 1 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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};
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};
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&spi {
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status = "okay";
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num-cs = <1>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <33000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x30000>;
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label = "u-boot";
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read-only;
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};
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partition@30000 {
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reg = <0x30000 0x10000>;
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label = "nvram";
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read-only;
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};
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partition@40000 {
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compatible = "denx,uimage";
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reg = <0x40000 0x3b0000>;
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label = "firmware";
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};
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partition@3f0000 {
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reg = <0x3f0000 0x10000>;
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label = "art";
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read-only;
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};
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};
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};
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};
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ð0 {
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status = "okay";
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};
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ð1 {
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status = "okay";
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};
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&pcie {
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status = "okay";
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ath9k: wifi@0,0 {
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compatible = "pci168c,002b";
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reg = <0x0000 0 0 0 0>;
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qca,no-eeprom;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&pinmux {
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switch_led_pins: pinmux_switch_led_pins {
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pinctrl-single,bits = <0x0 0x0 0xf8>;
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};
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};
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&uart {
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status = "okay";
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};
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