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https://github.com/openwrt/openwrt.git
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3a5584e0df
Adds latest 6.6 patches from the Raspberry Pi repository.
These patches were generated from:
https://github.com/raspberrypi/linux/commits/rpi-6.6.y/
With the following command:
git format-patch -N v6.6.67..HEAD
(HEAD -> 811ff707533bcd67cdcd368bbd46223082009b12)
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry picked from commit 692205305d)
51 lines
1.9 KiB
Diff
51 lines
1.9 KiB
Diff
From 0b4af929b7125abd3a262577b380c7c81ee9b1c5 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Mon, 11 Nov 2024 15:18:14 +0000
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Subject: [PATCH] dt: arm64: Fixup RP1 ethernet DT configuration
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Configure RP1's ethernet block to do the correct thing.
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clk_eth is intended to be fixed at 125MHz, so use a new compatible,
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and use assigned-clocks to configure the clock appropriately.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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arch/arm64/boot/dts/broadcom/rp1.dtsi | 10 +++++++---
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1 file changed, 7 insertions(+), 3 deletions(-)
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--- a/arch/arm64/boot/dts/broadcom/rp1.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/rp1.dtsi
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@@ -32,6 +32,7 @@
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// RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers
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<&rp1_clocks RP1_PLL_SYS>,
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<&rp1_clocks RP1_PLL_SYS_SEC>,
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+ <&rp1_clocks RP1_CLK_ETH>,
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<&rp1_clocks RP1_PLL_AUDIO>,
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<&rp1_clocks RP1_PLL_AUDIO_SEC>,
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<&rp1_clocks RP1_CLK_SYS>,
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@@ -46,6 +47,7 @@
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<1536000000>, // RP1_PLL_AUDIO_CORE
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<200000000>, // RP1_PLL_SYS
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<125000000>, // RP1_PLL_SYS_SEC
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+ <125000000>, // RP1_CLK_ETH
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<61440000>, // RP1_PLL_AUDIO
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<192000000>, // RP1_PLL_AUDIO_SEC
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<200000000>, // RP1_CLK_SYS
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@@ -976,12 +978,14 @@
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rp1_eth: ethernet@100000 {
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reg = <0xc0 0x40100000 0x0 0x4000>;
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- compatible = "cdns,macb";
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+ compatible = "raspberrypi,rp1-gem", "cdns,macb";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <RP1_INT_ETH IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&macb_pclk &macb_hclk &rp1_clocks RP1_CLK_ETH_TSU>;
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- clock-names = "pclk", "hclk", "tsu_clk";
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+ clocks = <&macb_pclk &macb_hclk
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+ &rp1_clocks RP1_CLK_ETH_TSU
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+ &rp1_clocks RP1_CLK_ETH>;
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+ clock-names = "pclk", "hclk", "tsu_clk", "tx_clk";
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phy-mode = "rgmii-id";
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cdns,aw2w-max-pipe = /bits/ 8 <8>;
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cdns,ar2r-max-pipe = /bits/ 8 <8>;
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