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9755f31edb
Enable testing kernel. Delete upstreamed patches: 0098-disable_cm.patch can be dropped, upstream fixed CM handling. Fix compile errors by using new kernel APIs. Fix fuzz by manually editing patches to ensure the code goes in the right place. For 721-NET-no-auto-carrier-off-support.patch, revert upstream commit a307593a6 to keep the OpenWrt ralink driver operational. Add mt7621-pci-phy patch to select REGMAP_MMIO as discussed in PR #3693 and #3952. Rename patches to follow the 3-digit classification from the OpenWrt Developer Guide. Run automatic quilt refresh. Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> Signed-off-by: maurerr <mariusd84@gmail.com>
86 lines
2.0 KiB
Diff
86 lines
2.0 KiB
Diff
From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 1 Apr 2020 02:07:59 +0800
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Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver
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This patch adds documentation for MediaTek MT7621 NAND flash controller
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driver.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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.../bindings/mtd/mediatek,mt7621-nfc.yaml | 68 ++++++++++++++++++++++
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1 file changed, 68 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
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@@ -0,0 +1,68 @@
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+# SPDX-License-Identifier: GPL-2.0
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding
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+
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+maintainers:
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+ - Weijie Gao <weijie.gao@mediatek.com>
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+
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+description: |
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+ This driver uses a single node to describe both NAND Flash controller
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+ interface (NFI) and ECC engine for MT7621 SoC.
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+ MT7621 supports only one chip select.
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+
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+properties:
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+ "#address-cells": false
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+ "#size-cells": false
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+
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+ compatible:
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+ enum:
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+ - mediatek,mt7621-nfc
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+
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+ reg:
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+ items:
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+ - description: Register base of NFI core
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+ - description: Register base of ECC engine
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+
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+ reg-names:
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+ items:
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+ - const: nfi
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+ - const: ecc
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+
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+ clocks:
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+ items:
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+ - description: Source clock for NFI core, fixed 125MHz
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+
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+ clock-names:
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+ items:
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+ - const: nfi_clk
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+
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+required:
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+ - compatible
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+ - reg
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+ - reg-names
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+ - clocks
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+ - clock-names
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+
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+examples:
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+ - |
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+ nficlock: nficlock {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+
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+ clock-frequency = <125000000>;
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+ };
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+
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+ nand@1e003000 {
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+ compatible = "mediatek,mt7621-nfc";
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+
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+ reg = <0x1e003000 0x800
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+ 0x1e003800 0x800>;
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+ reg-names = "nfi", "ecc";
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+
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+ clocks = <&nficlock>;
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+ clock-names = "nfi_clk";
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+ };
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