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9a417fbd0d
Refreshed all patches. Compile-tested on: ipq40xx, ramips Runtime-tested on: ipq40xx Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
68 lines
2.1 KiB
Diff
68 lines
2.1 KiB
Diff
From 788d269aee4c612d5cd97b896ea5d22f19137097 Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:34 +0800
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Subject: [PATCH 155/224] mmc: mediatek: add busy_check support
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bit7 of PATCH_BIT1 has different meaning in new design, to
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compatible with previous platform, clear this bit in new
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platform.
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/mtk-sd.c | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/drivers/mmc/host/mtk-sd.c
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+++ b/drivers/mmc/host/mtk-sd.c
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@@ -318,6 +318,7 @@ struct mtk_mmc_compatible {
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u32 pad_tune_reg;
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bool async_fifo;
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bool data_tune;
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+ bool busy_check;
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};
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struct msdc_tune_para {
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@@ -382,6 +383,7 @@ static const struct mtk_mmc_compatible m
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.pad_tune_reg = MSDC_PAD_TUNE,
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.async_fifo = false,
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.data_tune = false,
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+ .busy_check = false,
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};
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static const struct mtk_mmc_compatible mt8173_compat = {
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@@ -390,6 +392,7 @@ static const struct mtk_mmc_compatible m
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.pad_tune_reg = MSDC_PAD_TUNE,
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.async_fifo = false,
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.data_tune = false,
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+ .busy_check = false,
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};
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static const struct mtk_mmc_compatible mt2701_compat = {
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@@ -398,6 +401,7 @@ static const struct mtk_mmc_compatible m
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.pad_tune_reg = MSDC_PAD_TUNE0,
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.async_fifo = true,
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.data_tune = true,
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+ .busy_check = false,
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};
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static const struct mtk_mmc_compatible mt2712_compat = {
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@@ -406,6 +410,7 @@ static const struct mtk_mmc_compatible m
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.pad_tune_reg = MSDC_PAD_TUNE0,
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.async_fifo = true,
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.data_tune = true,
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+ .busy_check = true,
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};
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static const struct of_device_id msdc_of_ids[] = {
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@@ -1277,6 +1282,8 @@ static void msdc_init_hw(struct msdc_hos
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sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
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writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
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sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
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+ if (host->dev_comp->busy_check)
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+ sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
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if (host->dev_comp->async_fifo) {
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sdr_set_field(host->base + MSDC_PATCH_BIT2,
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MSDC_PB2_RESPWAIT, 3);
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