mirror of
https://github.com/openwrt/openwrt.git
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706a4ec40c
Manually rebased:
oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch
All other patches automatically rebased.
Build system: x86_64
Build-tested: ipq806x/R7800
Signed-off-by: John Audia <therealgraysky@proton.me>
113 lines
3.4 KiB
Diff
113 lines
3.4 KiB
Diff
From 9470174e7581e75a8ebd78964997314dfc2e706c Mon Sep 17 00:00:00 2001
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From: DENG Qingfang <dqfext@gmail.com>
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Date: Tue, 3 Nov 2020 13:06:18 +0800
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Subject: [PATCH] net: dsa: mt7530: support setting MTU
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MT7530/7531 has a global RX packet length register, which can be used
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to set MTU.
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Supported packet length values are 1522 (1518 if untagged), 1536,
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1552, and multiple of 1024 (from 2048 to 15360).
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Signed-off-by: DENG Qingfang <dqfext@gmail.com>
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Link: https://lore.kernel.org/r/20201103050618.11419-1-dqfext@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/dsa/mt7530.c | 49 ++++++++++++++++++++++++++++++++++++++++
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drivers/net/dsa/mt7530.h | 12 ++++++++++
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2 files changed, 61 insertions(+)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -1015,6 +1015,53 @@ mt7530_port_disable(struct dsa_switch *d
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mutex_unlock(&priv->reg_mutex);
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}
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+static int
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+mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
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+{
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+ struct mt7530_priv *priv = ds->priv;
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+ struct mii_bus *bus = priv->bus;
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+ int length;
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+ u32 val;
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+
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+ /* When a new MTU is set, DSA always set the CPU port's MTU to the
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+ * largest MTU of the slave ports. Because the switch only has a global
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+ * RX length register, only allowing CPU port here is enough.
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+ */
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+ if (!dsa_is_cpu_port(ds, port))
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+ return 0;
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+
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+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
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+
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+ val = mt7530_mii_read(priv, MT7530_GMACCR);
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+ val &= ~MAX_RX_PKT_LEN_MASK;
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+
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+ /* RX length also includes Ethernet header, MTK tag, and FCS length */
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+ length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
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+ if (length <= 1522) {
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+ val |= MAX_RX_PKT_LEN_1522;
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+ } else if (length <= 1536) {
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+ val |= MAX_RX_PKT_LEN_1536;
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+ } else if (length <= 1552) {
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+ val |= MAX_RX_PKT_LEN_1552;
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+ } else {
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+ val &= ~MAX_RX_JUMBO_MASK;
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+ val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
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+ val |= MAX_RX_PKT_LEN_JUMBO;
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+ }
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+
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+ mt7530_mii_write(priv, MT7530_GMACCR, val);
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+
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+ mutex_unlock(&bus->mdio_lock);
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+
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+ return 0;
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+}
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+
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+static int
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+mt7530_port_max_mtu(struct dsa_switch *ds, int port)
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+{
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+ return MT7530_MAX_MTU;
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+}
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+
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static void
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mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
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{
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@@ -2647,6 +2694,8 @@ static const struct dsa_switch_ops mt753
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.get_sset_count = mt7530_get_sset_count,
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.port_enable = mt7530_port_enable,
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.port_disable = mt7530_port_disable,
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+ .port_change_mtu = mt7530_port_change_mtu,
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+ .port_max_mtu = mt7530_port_max_mtu,
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.port_stp_state_set = mt7530_stp_state_set,
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.port_bridge_join = mt7530_port_bridge_join,
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.port_bridge_leave = mt7530_port_bridge_leave,
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -11,6 +11,9 @@
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#define MT7530_NUM_FDB_RECORDS 2048
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#define MT7530_ALL_MEMBERS 0xff
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+#define MTK_HDR_LEN 4
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+#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
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+
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enum mt753x_id {
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ID_MT7530 = 0,
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ID_MT7621 = 1,
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@@ -301,6 +304,15 @@ enum mt7530_vlan_port_attr {
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#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
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#define MT7531_DIS_CLR BIT(31)
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+#define MT7530_GMACCR 0x30e0
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+#define MAX_RX_JUMBO(x) ((x) << 2)
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+#define MAX_RX_JUMBO_MASK GENMASK(5, 2)
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+#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
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+#define MAX_RX_PKT_LEN_1522 0x0
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+#define MAX_RX_PKT_LEN_1536 0x1
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+#define MAX_RX_PKT_LEN_1552 0x2
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+#define MAX_RX_PKT_LEN_JUMBO 0x3
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+
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/* Register for MIB */
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#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
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#define MT7530_MIB_CCR 0x4fe0
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