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cf4520d15e
Sungbo Eo <mans0n@gorani.run> submitted another patch fixing an error
on reboot:
irqchip/versatile-fpga: Apply clear-mask earlier
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit 19af00850f)
59 lines
2.4 KiB
Diff
59 lines
2.4 KiB
Diff
From patchwork Sat Mar 21 13:38:42 2020
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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X-Patchwork-Submitter: Sungbo Eo <mans0n@gorani.run>
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X-Patchwork-Id: 11451163
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From: Sungbo Eo <mans0n@gorani.run>
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To: linux-oxnas@groups.io, Linus Walleij <linus.walleij@linaro.org>,
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Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>,
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Marc Zyngier <maz@kernel.org>, linux-arm-kernel@lists.infradead.org,
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linux-kernel@vger.kernel.org
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Subject: [PATCH] irqchip/versatile-fpga: Apply clear-mask earlier
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Date: Sat, 21 Mar 2020 22:38:42 +0900
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Message-Id: <20200321133842.2408823-1-mans0n@gorani.run>
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MIME-Version: 1.0
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Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
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Clear its own IRQs before the parent IRQ get enabled, so that the
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remaining IRQs do not accidentally interrupt the parent IRQ controller.
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This patch also fixes a reboot bug on OX820 SoC, where the remaining
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rps-timer IRQ raises a GIC interrupt that is left pending. After that,
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the rps-timer IRQ is cleared during driver initialization, and there's
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no IRQ left in rps-irq when local_irq_enable() is called, which evokes
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an error message "unexpected IRQ trap".
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Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT")
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Signed-off-by: Sungbo Eo <mans0n@gorani.run>
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Cc: Neil Armstrong <narmstrong@baylibre.com>
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Cc: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/irqchip/irq-versatile-fpga.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
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index 70e2cfff8175..f1386733d3bc 100644
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--- a/drivers/irqchip/irq-versatile-fpga.c
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+++ b/drivers/irqchip/irq-versatile-fpga.c
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@@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node *node,
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if (of_property_read_u32(node, "valid-mask", &valid_mask))
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valid_mask = 0;
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+ writel(clear_mask, base + IRQ_ENABLE_CLEAR);
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+ writel(clear_mask, base + FIQ_ENABLE_CLEAR);
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+
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/* Some chips are cascaded from a parent IRQ */
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq) {
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@@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct device_node *node,
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fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
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- writel(clear_mask, base + IRQ_ENABLE_CLEAR);
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- writel(clear_mask, base + FIQ_ENABLE_CLEAR);
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-
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/*
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* On Versatile AB/PB, some secondary interrupts have a direct
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* pass-thru to the primary controller for IRQs 20 and 22-31 which need
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