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d1954aa535
According to RTL8221B's datasheet, the PHY requires at least 10ms
for assert and 68ms (recommended) for de-assert. So increase the
assert/de-assert time to 15ms and 68ms respectively.
Fixes: c0c3234e17 ("mediatek: add support for JDCloud RE-CP-03")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/16106
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
346 lines
6.2 KiB
Plaintext
346 lines
6.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (C) 2023 Tianling Shen <cnsztl@immortalwrt.org>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "mt7986a.dtsi"
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/ {
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model = "JDCloud RE-CP-03";
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compatible = "jdcloud,re-cp-03", "mediatek,mt7986a";
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aliases {
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led-boot = &red_led;
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led-failsafe = &red_led;
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led-running = &green_led;
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led-upgrade = &green_led;
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serial0 = &uart0;
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};
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chosen {
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bootargs-override = "root=/dev/fit0 rootwait";
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stdout-path = "serial0:115200n8";
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rootdisk = <&emmc_rootdisk>;
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};
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memory@40000000 {
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reg = <0 0x40000000 0 0x40000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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button-joylink {
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label = "joylink";
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linux,code = <BTN_0>;
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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button-reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led-0 {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
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};
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red_led: led-1 {
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
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};
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green_led: led-2 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 12 GPIO_ACTIVE_LOW>;
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};
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&crypto {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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nvmem-cells = <&macaddr_factory_2a 0>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "2500base-x";
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phy-handle = <&phy6>;
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nvmem-cells = <&macaddr_factory_24 0>;
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nvmem-cell-names = "mac-address";
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&mdio {
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phy6: phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <6>;
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reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <68000>;
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realtek,aldps-enable;
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};
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switch: switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&mmc0 {
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bus-width = <8>;
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cap-mmc-highspeed;
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hs400-ds-delay = <0x14014>;
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max-frequency = <200000000>;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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status = "okay";
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card@0 {
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compatible = "mmc-card";
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reg = <0>;
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block {
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compatible = "block-device";
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partitions {
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block-partition-factory {
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partname = "factory";
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x1000>;
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};
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macaddr_factory_24: macaddr@24 {
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compatible = "mac-base";
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reg = <0x24 0x6>;
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#nvmem-cell-cells = <1>;
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};
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macaddr_factory_2a: macaddr@2a {
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compatible = "mac-base";
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reg = <0x2a 0x6>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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emmc_rootdisk: block-partition-production {
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partname = "production";
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};
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};
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};
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};
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};
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&pio {
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mmc0_pins_default: mmc0-pins-default {
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mux {
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function = "emmc";
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groups = "emmc_51";
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};
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conf-cmd-dat {
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pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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input-enable;
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drive-strength = <4>;
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mediatek,pull-up-adv = <1>;
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};
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conf-clk {
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pins = "EMMC_CK";
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drive-strength = <6>;
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mediatek,pull-down-adv = <2>;
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};
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conf-ds {
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pins = "EMMC_DSL";
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mediatek,pull-down-adv = <2>;
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};
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conf-rst {
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pins = "EMMC_RSTB";
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drive-strength = <4>;
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mediatek,pull-up-adv = <1>;
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};
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};
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mmc0_pins_uhs: mmc0-uhs-pins {
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mux {
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function = "emmc";
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groups = "emmc_51";
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};
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conf-cmd-dat {
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pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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input-enable;
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drive-strength = <4>;
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mediatek,pull-up-adv = <1>;
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};
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conf-clk {
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pins = "EMMC_CK";
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drive-strength = <6>;
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mediatek,pull-down-adv = <2>;
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};
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conf-ds {
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pins = "EMMC_DSL";
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mediatek,pull-down-adv = <2>;
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};
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conf-rst {
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pins = "EMMC_RSTB";
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drive-strength = <4>;
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mediatek,pull-up-adv = <1>;
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};
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};
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wf_2g_5g_pins: wf-2g-5g-pins {
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mux {
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function = "wifi";
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groups = "wf_2g", "wf_5g";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <4>;
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};
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};
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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&trng {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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pinctrl-names = "default";
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pinctrl-0 = <&wf_2g_5g_pins>;
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status = "okay";
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};
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