mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
64b53247c4
Refresh patches. Remove upstreamed patch: generic/pending/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch Update patches that no longer applies: generic/hack/901-debloat_sock_diag.patch Compile-tested on: x86/64. Runtime-tested on: x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
46 lines
1.3 KiB
Diff
46 lines
1.3 KiB
Diff
From 84b3092b3773777de1ba1ad142e53247fb881ddd Mon Sep 17 00:00:00 2001
|
|
From: Sean Wang <sean.wang@mediatek.com>
|
|
Date: Thu, 28 Dec 2017 18:00:11 +0800
|
|
Subject: [PATCH 215/224] arm64: dts: mt7622: turn uart0 clock to real ones
|
|
|
|
This patch also cleans up two oscillators that provide clocks for MT7623.
|
|
Switch the uart clocks to the real ones while at it.
|
|
|
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
|
Cc: Matthias Brugger <matthias.bgg@gmail.com>
|
|
---
|
|
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 ++-------------
|
|
1 file changed, 2 insertions(+), 13 deletions(-)
|
|
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
|
@@ -91,18 +91,6 @@
|
|
};
|
|
};
|
|
|
|
- uart_clk: dummy25m {
|
|
- compatible = "fixed-clock";
|
|
- #clock-cells = <0>;
|
|
- clock-frequency = <25000000>;
|
|
- };
|
|
-
|
|
- bus_clk: dummy280m {
|
|
- compatible = "fixed-clock";
|
|
- #clock-cells = <0>;
|
|
- clock-frequency = <280000000>;
|
|
- };
|
|
-
|
|
pwrap_clk: dummy40m {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <40000000>;
|
|
@@ -234,7 +222,8 @@
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x400>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
|
|
- clocks = <&uart_clk>, <&bus_clk>;
|
|
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
|
|
+ <&pericfg CLK_PERI_UART1_PD>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|