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https://github.com/openwrt/openwrt.git
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95d3d353f8
Copy patches from patches-6.1 to patches-6.6. No changes. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
270 lines
9.9 KiB
Diff
270 lines
9.9 KiB
Diff
From d35469096915f2551ed1d26da1ab12ff500fc963 Mon Sep 17 00:00:00 2001
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From: Maso Huang <maso.huang@mediatek.com>
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Date: Thu, 17 Aug 2023 18:13:33 +0800
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Subject: [PATCH 1/9] ASoC: mediatek: mt7986: add common header
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Add header files for register definition and structure.
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Signed-off-by: Maso Huang <maso.huang@mediatek.com>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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sound/soc/mediatek/mt7986/mt7986-afe-common.h | 49 +++++
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sound/soc/mediatek/mt7986/mt7986-reg.h | 196 ++++++++++++++++++
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2 files changed, 245 insertions(+)
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create mode 100644 sound/soc/mediatek/mt7986/mt7986-afe-common.h
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create mode 100644 sound/soc/mediatek/mt7986/mt7986-reg.h
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--- /dev/null
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+++ b/sound/soc/mediatek/mt7986/mt7986-afe-common.h
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@@ -0,0 +1,49 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * mt7986-afe-common.h -- MediaTek 7986 audio driver definitions
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+ *
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+ * Copyright (c) 2023 MediaTek Inc.
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+ * Authors: Vic Wu <vic.wu@mediatek.com>
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+ * Maso Huang <maso.huang@mediatek.com>
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+ */
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+
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+#ifndef _MT_7986_AFE_COMMON_H_
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+#define _MT_7986_AFE_COMMON_H_
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+
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+#include <sound/soc.h>
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+#include <linux/clk.h>
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+#include <linux/list.h>
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+#include <linux/regmap.h>
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+#include "../common/mtk-base-afe.h"
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+
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+enum {
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+ MT7986_MEMIF_DL1,
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+ MT7986_MEMIF_VUL12,
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+ MT7986_MEMIF_NUM,
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+ MT7986_DAI_ETDM = MT7986_MEMIF_NUM,
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+ MT7986_DAI_NUM,
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+};
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+
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+enum {
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+ MT7986_IRQ_0,
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+ MT7986_IRQ_1,
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+ MT7986_IRQ_2,
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+ MT7986_IRQ_NUM,
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+};
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+
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+struct mt7986_afe_private {
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+ struct clk_bulk_data *clks;
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+ int num_clks;
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+
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+ int pm_runtime_bypass_reg_ctl;
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+
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+ /* dai */
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+ void *dai_priv[MT7986_DAI_NUM];
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+};
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+
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+unsigned int mt7986_afe_rate_transform(struct device *dev,
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+ unsigned int rate);
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+
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+/* dai register */
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+int mt7986_dai_etdm_register(struct mtk_base_afe *afe);
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+#endif
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--- /dev/null
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+++ b/sound/soc/mediatek/mt7986/mt7986-reg.h
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@@ -0,0 +1,196 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * mt7986-reg.h -- MediaTek 7986 audio driver reg definition
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+ *
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+ * Copyright (c) 2023 MediaTek Inc.
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+ * Authors: Vic Wu <vic.wu@mediatek.com>
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+ * Maso Huang <maso.huang@mediatek.com>
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+ */
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+
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+#ifndef _MT7986_REG_H_
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+#define _MT7986_REG_H_
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+
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+#define AUDIO_TOP_CON2 0x0008
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+#define AUDIO_TOP_CON4 0x0010
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+#define AUDIO_ENGEN_CON0 0x0014
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+#define AFE_IRQ_MCU_EN 0x0100
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+#define AFE_IRQ_MCU_STATUS 0x0120
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+#define AFE_IRQ_MCU_CLR 0x0128
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+#define AFE_IRQ0_MCU_CFG0 0x0140
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+#define AFE_IRQ0_MCU_CFG1 0x0144
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+#define AFE_IRQ1_MCU_CFG0 0x0148
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+#define AFE_IRQ1_MCU_CFG1 0x014c
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+#define AFE_IRQ2_MCU_CFG0 0x0150
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+#define AFE_IRQ2_MCU_CFG1 0x0154
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+#define ETDM_IN5_CON0 0x13f0
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+#define ETDM_IN5_CON1 0x13f4
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+#define ETDM_IN5_CON2 0x13f8
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+#define ETDM_IN5_CON3 0x13fc
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+#define ETDM_IN5_CON4 0x1400
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+#define ETDM_OUT5_CON0 0x1570
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+#define ETDM_OUT5_CON4 0x1580
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+#define ETDM_OUT5_CON5 0x1584
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+#define ETDM_4_7_COWORK_CON0 0x15e0
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+#define ETDM_4_7_COWORK_CON1 0x15e4
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+#define AFE_CONN018_1 0x1b44
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+#define AFE_CONN018_4 0x1b50
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+#define AFE_CONN019_1 0x1b64
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+#define AFE_CONN019_4 0x1b70
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+#define AFE_CONN124_1 0x2884
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+#define AFE_CONN124_4 0x2890
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+#define AFE_CONN125_1 0x28a4
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+#define AFE_CONN125_4 0x28b0
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+#define AFE_CONN_RS_0 0x3920
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+#define AFE_CONN_RS_3 0x392c
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+#define AFE_CONN_16BIT_0 0x3960
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+#define AFE_CONN_16BIT_3 0x396c
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+#define AFE_CONN_24BIT_0 0x3980
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+#define AFE_CONN_24BIT_3 0x398c
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+#define AFE_MEMIF_CON0 0x3d98
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+#define AFE_MEMIF_RD_MON 0x3da0
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+#define AFE_MEMIF_WR_MON 0x3da4
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+#define AFE_DL0_BASE_MSB 0x3e40
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+#define AFE_DL0_BASE 0x3e44
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+#define AFE_DL0_CUR_MSB 0x3e48
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+#define AFE_DL0_CUR 0x3e4c
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+#define AFE_DL0_END_MSB 0x3e50
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+#define AFE_DL0_END 0x3e54
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+#define AFE_DL0_RCH_MON 0x3e58
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+#define AFE_DL0_LCH_MON 0x3e5c
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+#define AFE_DL0_CON0 0x3e60
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+#define AFE_VUL0_BASE_MSB 0x4220
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+#define AFE_VUL0_BASE 0x4224
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+#define AFE_VUL0_CUR_MSB 0x4228
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+#define AFE_VUL0_CUR 0x422c
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+#define AFE_VUL0_END_MSB 0x4230
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+#define AFE_VUL0_END 0x4234
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+#define AFE_VUL0_CON0 0x4238
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+
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+#define AFE_MAX_REGISTER AFE_VUL0_CON0
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+#define AFE_IRQ_STATUS_BITS 0x7
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+#define AFE_IRQ_CNT_SHIFT 0
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+#define AFE_IRQ_CNT_MASK 0xffffff
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+
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+/* AUDIO_TOP_CON2 */
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+#define CLK_OUT5_PDN BIT(14)
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+#define CLK_OUT5_PDN_MASK BIT(14)
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+#define CLK_IN5_PDN BIT(7)
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+#define CLK_IN5_PDN_MASK BIT(7)
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+
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+/* AUDIO_TOP_CON4 */
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+#define PDN_APLL_TUNER2 BIT(12)
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+#define PDN_APLL_TUNER2_MASK BIT(12)
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+
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+/* AUDIO_ENGEN_CON0 */
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+#define AUD_APLL2_EN BIT(3)
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+#define AUD_APLL2_EN_MASK BIT(3)
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+#define AUD_26M_EN BIT(0)
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+#define AUD_26M_EN_MASK BIT(0)
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+
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+/* AFE_DL0_CON0 */
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+#define DL0_ON_SFT 28
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+#define DL0_ON_MASK 0x1
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+#define DL0_ON_MASK_SFT BIT(28)
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+#define DL0_MINLEN_SFT 20
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+#define DL0_MINLEN_MASK 0xf
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+#define DL0_MINLEN_MASK_SFT (0xf << 20)
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+#define DL0_MODE_SFT 8
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+#define DL0_MODE_MASK 0x1f
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+#define DL0_MODE_MASK_SFT (0x1f << 8)
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+#define DL0_PBUF_SIZE_SFT 5
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+#define DL0_PBUF_SIZE_MASK 0x3
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+#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5)
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+#define DL0_MONO_SFT 4
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+#define DL0_MONO_MASK 0x1
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+#define DL0_MONO_MASK_SFT BIT(4)
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+#define DL0_HALIGN_SFT 2
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+#define DL0_HALIGN_MASK 0x1
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+#define DL0_HALIGN_MASK_SFT BIT(2)
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+#define DL0_HD_MODE_SFT 0
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+#define DL0_HD_MODE_MASK 0x3
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+#define DL0_HD_MODE_MASK_SFT (0x3 << 0)
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+
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+/* AFE_VUL0_CON0 */
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+#define VUL0_ON_SFT 28
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+#define VUL0_ON_MASK 0x1
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+#define VUL0_ON_MASK_SFT BIT(28)
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+#define VUL0_MODE_SFT 8
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+#define VUL0_MODE_MASK 0x1f
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+#define VUL0_MODE_MASK_SFT (0x1f << 8)
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+#define VUL0_MONO_SFT 4
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+#define VUL0_MONO_MASK 0x1
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+#define VUL0_MONO_MASK_SFT BIT(4)
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+#define VUL0_HALIGN_SFT 2
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+#define VUL0_HALIGN_MASK 0x1
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+#define VUL0_HALIGN_MASK_SFT BIT(2)
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+#define VUL0_HD_MODE_SFT 0
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+#define VUL0_HD_MODE_MASK 0x3
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+#define VUL0_HD_MODE_MASK_SFT (0x3 << 0)
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+
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+/* AFE_IRQ_MCU_CON */
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+#define IRQ_MCU_MODE_SFT 4
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+#define IRQ_MCU_MODE_MASK 0x1f
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+#define IRQ_MCU_MODE_MASK_SFT (0x1f << 4)
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+#define IRQ_MCU_ON_SFT 0
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+#define IRQ_MCU_ON_MASK 0x1
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+#define IRQ_MCU_ON_MASK_SFT BIT(0)
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+#define IRQ0_MCU_CLR_SFT 0
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+#define IRQ0_MCU_CLR_MASK 0x1
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+#define IRQ0_MCU_CLR_MASK_SFT BIT(0)
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+#define IRQ1_MCU_CLR_SFT 1
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+#define IRQ1_MCU_CLR_MASK 0x1
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+#define IRQ1_MCU_CLR_MASK_SFT BIT(1)
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+#define IRQ2_MCU_CLR_SFT 2
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+#define IRQ2_MCU_CLR_MASK 0x1
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+#define IRQ2_MCU_CLR_MASK_SFT BIT(2)
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+
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+/* ETDM_IN5_CON2 */
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+#define IN_CLK_SRC(x) ((x) << 10)
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+#define IN_CLK_SRC_SFT 10
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+#define IN_CLK_SRC_MASK GENMASK(12, 10)
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+
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+/* ETDM_IN5_CON3 */
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+#define IN_SEL_FS(x) ((x) << 26)
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+#define IN_SEL_FS_SFT 26
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+#define IN_SEL_FS_MASK GENMASK(30, 26)
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+
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+/* ETDM_IN5_CON4 */
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+#define IN_RELATCH(x) ((x) << 20)
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+#define IN_RELATCH_SFT 20
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+#define IN_RELATCH_MASK GENMASK(24, 20)
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+#define IN_CLK_INV BIT(18)
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+#define IN_CLK_INV_MASK BIT(18)
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+
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+/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
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+#define RELATCH_SRC_MASK GENMASK(30, 28)
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+#define ETDM_CH_NUM_MASK GENMASK(27, 23)
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+#define ETDM_WRD_LEN_MASK GENMASK(20, 16)
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+#define ETDM_BIT_LEN_MASK GENMASK(15, 11)
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+#define ETDM_FMT_MASK GENMASK(8, 6)
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+#define ETDM_SYNC BIT(1)
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+#define ETDM_SYNC_MASK BIT(1)
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+#define ETDM_EN BIT(0)
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+#define ETDM_EN_MASK BIT(0)
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+
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+/* ETDM_OUT5_CON4 */
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+#define OUT_RELATCH(x) ((x) << 24)
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+#define OUT_RELATCH_SFT 24
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+#define OUT_RELATCH_MASK GENMASK(28, 24)
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+#define OUT_CLK_SRC(x) ((x) << 6)
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+#define OUT_CLK_SRC_SFT 6
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+#define OUT_CLK_SRC_MASK GENMASK(8, 6)
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+#define OUT_SEL_FS(x) (x)
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+#define OUT_SEL_FS_SFT 0
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+#define OUT_SEL_FS_MASK GENMASK(4, 0)
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+
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+/* ETDM_OUT5_CON5 */
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+#define ETDM_CLK_DIV BIT(12)
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+#define ETDM_CLK_DIV_MASK BIT(12)
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+#define OUT_CLK_INV BIT(9)
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+#define OUT_CLK_INV_MASK BIT(9)
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+
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+/* ETDM_4_7_COWORK_CON0 */
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+#define OUT_SEL(x) ((x) << 12)
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+#define OUT_SEL_SFT 12
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+#define OUT_SEL_MASK GENMASK(15, 12)
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+#endif
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