mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 23:42:43 +00:00
255268ce1a
xrx200 max MTU is reduced so that it works correctly when set to the max, and the max MTU of the switch is increased to match. In 5.10, the switch driver now enables non-standard MTUs on a per-port basis, with the overall frame size set based on the cpu port. When the MTU is not used, this should have no effect. The maximum packet size is limited as large packets cause the switch to lock up. 0702-net-lantiq-add-support-for-jumbo-frames.patch comes from net-next commit 998ac358019e491217e752bc6dcbb3afb2a6fa3e. In 5.4, all switch ports are configured to accept the max MTU, as 5.4 does not have port_max_mtu/port_change_mtu callbacks. Signed-off-by: Thomas Nixon <tom@tomn.co.uk>
127 lines
3.9 KiB
Diff
127 lines
3.9 KiB
Diff
From 14d4e308e0aa0b78dc7a059716861a4380de3535 Mon Sep 17 00:00:00 2001
|
|
From: Aleksander Jan Bajkowski <olek2@wp.pl>
|
|
Date: Tue, 14 Sep 2021 23:21:02 +0200
|
|
Subject: [PATCH 5/5] net: lantiq: configure the burst length in ethernet
|
|
drivers
|
|
|
|
Configure the burst length in Ethernet drivers. This improves
|
|
Ethernet performance by 58%. According to the vendor BSP,
|
|
8W burst length is supported by ar9 and newer SoCs.
|
|
|
|
The NAT benchmark results on xRX200 (Down/Up):
|
|
* 2W: 330 Mb/s
|
|
* 4W: 432 Mb/s 372 Mb/s
|
|
* 8W: 520 Mb/s 389 Mb/s
|
|
|
|
Tested on xRX200 and xRX330.
|
|
|
|
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
drivers/net/ethernet/lantiq_etop.c | 21 ++++++++++++++++++---
|
|
drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++---
|
|
2 files changed, 36 insertions(+), 6 deletions(-)
|
|
|
|
--- a/drivers/net/ethernet/lantiq_etop.c
|
|
+++ b/drivers/net/ethernet/lantiq_etop.c
|
|
@@ -148,6 +148,9 @@ struct ltq_etop_priv {
|
|
struct ltq_etop_chan txch;
|
|
struct ltq_etop_chan rxch;
|
|
|
|
+ int tx_burst_len;
|
|
+ int rx_burst_len;
|
|
+
|
|
int tx_irq;
|
|
int rx_irq;
|
|
|
|
@@ -399,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev
|
|
int rx = priv->rx_irq - LTQ_DMA_ETOP;
|
|
int err;
|
|
|
|
- ltq_dma_init_port(DMA_PORT_ETOP);
|
|
+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);
|
|
|
|
priv->txch.dma.nr = tx;
|
|
priv->txch.dma.dev = &priv->pdev->dev;
|
|
@@ -676,8 +679,8 @@ ltq_etop_tx(struct sk_buff *skb, struct
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
|
|
- /* dma needs to start on a 16 byte aligned address */
|
|
- byte_offset = CPHYSADDR(skb->data) % 16;
|
|
+ /* dma needs to start on a burst length value aligned address */
|
|
+ byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
|
|
priv->txch.skb[priv->txch.dma.desc] = skb;
|
|
|
|
netif_trans_update(dev);
|
|
@@ -925,6 +928,18 @@ static int ltq_etop_probe(struct platfor
|
|
spin_lock_init(&priv->lock);
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
+ err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
|
|
+ if (err < 0) {
|
|
+ dev_err(&pdev->dev, "unable to read tx-burst-length property\n");
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
|
|
+ if (err < 0) {
|
|
+ dev_err(&pdev->dev, "unable to read rx-burst-length property\n");
|
|
+ return err;
|
|
+ }
|
|
+
|
|
netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
|
|
netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
|
|
priv->txch.netdev = dev;
|
|
--- a/drivers/net/ethernet/lantiq_xrx200.c
|
|
+++ b/drivers/net/ethernet/lantiq_xrx200.c
|
|
@@ -81,6 +81,9 @@ struct xrx200_priv {
|
|
struct net_device *net_dev;
|
|
struct device *dev;
|
|
|
|
+ int tx_burst_len;
|
|
+ int rx_burst_len;
|
|
+
|
|
__iomem void *pmac_reg;
|
|
};
|
|
|
|
@@ -363,8 +366,8 @@ static netdev_tx_t xrx200_start_xmit(str
|
|
if (unlikely(dma_mapping_error(priv->dev, mapping)))
|
|
goto err_drop;
|
|
|
|
- /* dma needs to start on a 16 byte aligned address */
|
|
- byte_offset = mapping % 16;
|
|
+ /* dma needs to start on a burst length value aligned address */
|
|
+ byte_offset = mapping % (priv->tx_burst_len * 4);
|
|
|
|
desc->addr = mapping - byte_offset;
|
|
/* Make sure the address is written before we give it to HW */
|
|
@@ -465,7 +468,7 @@ static int xrx200_dma_init(struct xrx200
|
|
int ret = 0;
|
|
int i;
|
|
|
|
- ltq_dma_init_port(DMA_PORT_ETOP);
|
|
+ ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);
|
|
|
|
ch_rx->dma.nr = XRX200_DMA_RX;
|
|
ch_rx->dma.dev = priv->dev;
|
|
@@ -584,6 +587,18 @@ static int xrx200_probe(struct platform_
|
|
if (err)
|
|
eth_hw_addr_random(net_dev);
|
|
|
|
+ err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
|
|
+ if (err < 0) {
|
|
+ dev_err(dev, "unable to read tx-burst-length property\n");
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
|
|
+ if (err < 0) {
|
|
+ dev_err(dev, "unable to read rx-burst-length property\n");
|
|
+ return err;
|
|
+ }
|
|
+
|
|
/* bring up the dma engine and IP core */
|
|
err = xrx200_dma_init(priv);
|
|
if (err)
|