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8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
140 lines
3.6 KiB
Diff
140 lines
3.6 KiB
Diff
From 0328374ae09c7856e06a63af0c065822474a2985 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Wed, 15 Nov 2023 14:48:43 +0000
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Subject: [PATCH 0825/1085] ARM: dts: Add BCM2712 D0 dts
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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.../boot/dts/broadcom/bcm2712d0-rpi-5-b.dts | 107 ++++++++++++++++++
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arch/arm64/boot/dts/broadcom/Makefile | 1 +
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.../boot/dts/broadcom/bcm2712d0-rpi-5-b.dts | 2 +
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3 files changed, 110 insertions(+)
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create mode 100644 arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
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create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
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--- /dev/null
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+++ b/arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
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@@ -0,0 +1,107 @@
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+// SPDX-License-Identifier: GPL-2.0
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+#include "bcm2712-rpi-5-b.dts"
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+
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+&gio {
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+ brcm,gpio-bank-widths = <32 4>;
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+
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+ gpio-line-names =
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+ "", // GPIO_000
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+ "2712_BOOT_CS_N", // GPIO_001
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+ "2712_BOOT_MISO", // GPIO_002
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+ "2712_BOOT_MOSI", // GPIO_003
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+ "2712_BOOT_SCLK", // GPIO_004
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+ "", // GPIO_005
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+ "", // GPIO_006
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+ "", // GPIO_007
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+ "", // GPIO_008
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+ "", // GPIO_009
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+ "", // GPIO_010
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+ "", // GPIO_011
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+ "", // GPIO_012
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+ "", // GPIO_013
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+ "PCIE_SDA", // GPIO_014
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+ "PCIE_SCL", // GPIO_015
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+ "", // GPIO_016
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+ "", // GPIO_017
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+ "-", // GPIO_018
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+ "-", // GPIO_019
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+ "PWR_GPIO", // GPIO_020
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+ "2712_G21_FS", // GPIO_021
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+ "-", // GPIO_022
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+ "-", // GPIO_023
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+ "BT_RTS", // GPIO_024
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+ "BT_CTS", // GPIO_025
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+ "BT_TXD", // GPIO_026
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+ "BT_RXD", // GPIO_027
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+ "WL_ON", // GPIO_028
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+ "BT_ON", // GPIO_029
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+ "WIFI_SDIO_CLK", // GPIO_030
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+ "WIFI_SDIO_CMD", // GPIO_031
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+ "WIFI_SDIO_D0", // GPIO_032
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+ "WIFI_SDIO_D1", // GPIO_033
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+ "WIFI_SDIO_D2", // GPIO_034
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+ "WIFI_SDIO_D3"; // GPIO_035
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+};
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+
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+&gio_aon {
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+ brcm,gpio-bank-widths = <15 6>;
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+
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+ gpio-line-names =
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+ "RP1_SDA", // AON_GPIO_00
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+ "RP1_SCL", // AON_GPIO_01
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+ "RP1_RUN", // AON_GPIO_02
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+ "SD_IOVDD_SEL", // AON_GPIO_03
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+ "SD_PWR_ON", // AON_GPIO_04
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+ "SD_CDET_N", // AON_GPIO_05
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+ "SD_FLG_N", // AON_GPIO_06
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+ "", // AON_GPIO_07
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+ "2712_WAKE", // AON_GPIO_08
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+ "2712_STAT_LED", // AON_GPIO_09
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+ "", // AON_GPIO_10
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+ "", // AON_GPIO_11
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+ "PMIC_INT", // AON_GPIO_12
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+ "UART_TX_FS", // AON_GPIO_13
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+ "UART_RX_FS", // AON_GPIO_14
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+ "", // AON_GPIO_15
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+ "", // AON_GPIO_16
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+
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+ // Pad bank0 out to 32 entries
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+ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",
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+
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+ "HDMI0_SCL", // AON_SGPIO_00
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+ "HDMI0_SDA", // AON_SGPIO_01
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+ "HDMI1_SCL", // AON_SGPIO_02
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+ "HDMI1_SDA", // AON_SGPIO_03
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+ "PMIC_SCL", // AON_SGPIO_04
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+ "PMIC_SDA"; // AON_SGPIO_05
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+};
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+
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+&pinctrl {
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+ compatible = "brcm,bcm2712d0-pinctrl";
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+ reg = <0x7d504100 0x20>;
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+};
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+
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+&pinctrl_aon {
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+ compatible = "brcm,bcm2712d0-aon-pinctrl";
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+ reg = <0x7d510700 0x1c>;
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+};
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+
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+&vc4 {
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+ compatible = "brcm,bcm2712d0-vc6";
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+};
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+
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+&uart10 {
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+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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+};
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+
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+&spi10 {
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+ dmas = <&dma40 3>, <&dma40 4>;
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+};
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+
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+&hdmi0 {
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+ dmas = <&dma40 (12|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
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+};
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+
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+&hdmi1 {
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+ dmas = <&dma40 (13|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
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+};
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--- a/arch/arm64/boot/dts/broadcom/Makefile
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+++ b/arch/arm64/boot/dts/broadcom/Makefile
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@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rp
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4s.dtb
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-5-b.dtb
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+dtb-$(CONFIG_ARCH_BCM2835) += bcm2712d0-rpi-5-b.dtb
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subdir-y += bcmbca
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subdir-y += northstar2
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--- /dev/null
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+++ b/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts
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@@ -0,0 +1,2 @@
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+// SPDX-License-Identifier: GPL-2.0
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+#include "../../../../arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts"
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