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Radxa ROCK Pi S is a small in size, full in features SBC[1] using the Rockchip RK3308B SoC. Hardware -------- - Rockchip RK3308B SoC - Quad A35 CPU - 256/512MB DDR3 RAM - Optional 4/8GB eMMC - Micro SD Card slot - Optional WiFi 4 and BT 4 (not supported yet) - 1x 100M Ethernet with PoE support (additional PoE HAT required) - 1x USB 2.0 Type-A port (Host) - 1x USB 2.0 Type-C port (OTG) - 2x 26 Pin GPIO header [1] https://radxa.com/products/rockpi/pis Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://github.com/openwrt/openwrt/pull/15933 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
85 lines
2.7 KiB
Diff
85 lines
2.7 KiB
Diff
From c45de75d7a9ab44a15dedc7a121d6371d6891301 Mon Sep 17 00:00:00 2001
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From: Trevor Woerner <twoerner@gmail.com>
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Date: Mon, 20 Nov 2023 11:22:32 -0500
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Subject: [PATCH] arm64: dts: rockchip: add gpio-line-names to rk3308-rock-pi-s
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Add names to the pins of the general-purpose expansion header as given in the
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Radxa GPIO page[1] following the conventions in the kernel documentation[2] to
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make it easier for users to correlate the pins with functions when using
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utilities such as gpioinfo.
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[1] https://wiki.radxa.com/RockpiS/hardware/gpio
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[2] Documentation/devicetree/bindings/gpio/gpio.txt
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Signed-off-by: Trevor Woerner <twoerner@gmail.com>
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Link: https://lore.kernel.org/r/20231120162232.27653-1-twoerner@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3308-rock-pi-s.dts | 58 +++++++++++++++++++
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1 file changed, 58 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
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@@ -258,3 +258,61 @@
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&wdt {
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status = "okay";
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};
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+
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+&gpio0 {
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+ gpio-line-names =
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+ /* GPIO0_A0 - A7 */
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+ "", "", "", "", "", "", "", "",
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+ /* GPIO0_B0 - B7 */
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+ "", "", "", "header1-pin3 [GPIO0_B3]", "header1-pin5 [GPIO0_B4]",
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+ "", "", "header1-pin11 [GPIO0_B7]",
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+ /* GPIO0_C0 - C7 */
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+ "header1-pin13 [GPIO0_C0]", "header1-pin15 [GPIO0_C1]", "", "", "",
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+ "", "", "",
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+ /* GPIO0_D0 - D8 */
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+ "", "", "", "", "", "", "", "";
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+};
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+
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+&gpio1 {
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+ gpio-line-names =
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+ /* GPIO1_A0 - A7 */
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+ "", "", "", "", "", "", "", "",
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+ /* GPIO1_B0 - B7 */
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+ "", "", "", "", "", "", "", "",
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+ /* GPIO1_C0 - C7 */
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+ "", "", "", "", "", "", "header1-pin21 [GPIO1_C6]",
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+ "header1-pin19 [GPIO1_C7]",
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+ /* GPIO1_D0 - D8 */
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+ "header1-pin23 [GPIO1_D0]", "header1-pin24 [GPIO1_D1]", "", "", "",
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+ "", "", "";
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+};
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+
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+&gpio2 {
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+ gpio-line-names =
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+ /* GPIO2_A0 - A7 */
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+ "header1-pin10 [GPIO2_A0]", "header1-pin8 [GPIO2_A1]", "", "",
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+ "header1-pin7 [GPIO2_A4]", "header1-pin12 [GPIO2_A5]",
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+ "header2-pin46 [GPIO2_A6]", "header1-pin22 [GPIO1_A7]",
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+ /* GPIO2_B0 - B7 */
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+ "header2-pin45 [GPIO2_B0]", "header1-pin18 [GPIO2_B1]",
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+ "header1-pin16 [GPIO2_B2]", "header2-pin44 [GPIO2_B3]",
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+ "header2-pin43 [GPIO2_B4]", "header2-pin28 [GPIO2_B5]",
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+ "header2-pin30 [GPIO2_B6]", "header2-pin32 [GPIO2_B7]",
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+ /* GPIO2_C0 - C7 */
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+ "header2-pin34 [GPIO2_C0]", "", "", "", "", "", "", "",
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+ /* GPIO2_D0 - D8 */
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+ "", "", "", "", "", "", "", "";
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+};
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+
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+&gpio3 {
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+ gpio-line-names =
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+ /* GPIO3_A0 - A7 */
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+ "", "", "", "", "", "", "", "",
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+ /* GPIO3_B0 - B7 */
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+ "", "", "header2-pin42 [GPIO3_B2]", "header2-pin41 [GPIO3_B3]",
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+ "header2-pin40 [GPIO3_B4]", "header2-pin39 [GPIO3_B5]", "", "",
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+ /* GPIO3_C0 - C7 */
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+ "", "", "", "", "", "", "", "",
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+ /* GPIO3_D0 - D8 */
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+ "", "", "", "", "", "", "", "";
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+};
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