mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 06:08:08 +00:00
93dd2f7211
- Rebased the patches for 4.14 - Dropped spi-qup and 0027, 0028, 0029 clk patches since it's already included in upstream. Tested on IPQ AP148 Board: 1) NOR boot and NAND boot 2) Tested USB and PCIe interfaces 3) WDOG test 4) cpu frequency scaling 5) ethernet, 2G and 5G WiFi 6) ubi sysupgrade Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>
115 lines
4.1 KiB
Diff
115 lines
4.1 KiB
Diff
From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001
|
|
From: Sham Muthayyan <smuthayy@codeaurora.org>
|
|
Date: Tue, 26 Jul 2016 12:28:31 +0530
|
|
Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x
|
|
|
|
Resolved PCIE EP detection errors caused due to missing iATU programming.
|
|
|
|
Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe
|
|
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
|
|
---
|
|
drivers/pci/host/pcie-qcom.c | 77 ++++++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 77 insertions(+)
|
|
|
|
--- a/drivers/pci/dwc/pcie-qcom.c
|
|
+++ b/drivers/pci/dwc/pcie-qcom.c
|
|
@@ -83,6 +83,30 @@
|
|
#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
|
|
#define PCIE_CAP_LINK1_VAL 0x2FD7F
|
|
|
|
+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
|
|
+
|
|
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
|
|
+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
|
|
+
|
|
+#define PCIE20_PLR_IATU_VIEWPORT 0x900
|
|
+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
|
|
+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
|
|
+
|
|
+#define PCIE20_PLR_IATU_CTRL1 0x904
|
|
+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
|
|
+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
|
|
+
|
|
+#define PCIE20_PLR_IATU_CTRL2 0x908
|
|
+#define PCIE20_PLR_IATU_ENABLE BIT(31)
|
|
+
|
|
+#define PCIE20_PLR_IATU_LBAR 0x90C
|
|
+#define PCIE20_PLR_IATU_UBAR 0x910
|
|
+#define PCIE20_PLR_IATU_LAR 0x914
|
|
+#define PCIE20_PLR_IATU_LTAR 0x918
|
|
+#define PCIE20_PLR_IATU_UTAR 0x91c
|
|
+
|
|
+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
|
|
+
|
|
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
|
|
|
|
#define PCIE20_MISC_CONTROL_1_REG 0x8BC
|
|
@@ -251,6 +275,57 @@
|
|
writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
|
|
}
|
|
|
|
+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
|
|
+{
|
|
+ struct pcie_port *pp = &pcie->pci->pp;
|
|
+
|
|
+ /*
|
|
+ * program and enable address translation region 0 (device config
|
|
+ * address space); region type config;
|
|
+ * axi config address range to device config address range
|
|
+ */
|
|
+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
|
|
+ PCIE20_PLR_IATU_REGION_INDEX(0),
|
|
+ pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT);
|
|
+
|
|
+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1);
|
|
+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2);
|
|
+ writel(pp->cfg0_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR);
|
|
+ writel((pp->cfg0_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR);
|
|
+ writel((pp->cfg0_base + pp->cfg0_size - 1),
|
|
+ pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR);
|
|
+ writel(busdev, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR);
|
|
+ writel(0, pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR);
|
|
+}
|
|
+
|
|
+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
|
|
+{
|
|
+ struct pcie_port *pp = &pcie->pci->pp;
|
|
+
|
|
+ /*
|
|
+ * program and enable address translation region 2 (device resource
|
|
+ * address space); region type memory;
|
|
+ * axi device bar address range to device bar address range
|
|
+ */
|
|
+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
|
|
+ PCIE20_PLR_IATU_REGION_INDEX(2),
|
|
+ pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT);
|
|
+
|
|
+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1);
|
|
+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2);
|
|
+ writel(pp->mem_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR);
|
|
+ writel((pp->mem_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR);
|
|
+ writel(pp->mem_base + pp->mem_size - 1,
|
|
+ pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR);
|
|
+ writel(pp->mem_bus_addr, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR);
|
|
+ writel(upper_32_bits(pp->mem_bus_addr),
|
|
+ pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR);
|
|
+
|
|
+ /* 256B PCIE buffer setting */
|
|
+ writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
|
|
+ writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
|
|
+}
|
|
+
|
|
static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
|
|
{
|
|
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
|
|
@@ -465,6 +538,9 @@
|
|
writel(CFG_BRIDGE_SB_INIT,
|
|
pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
|
|
|
|
+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
|
|
+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
|
|
+
|
|
return 0;
|
|
|
|
err_deassert_ahb:
|