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7bf62e2451
All patches automatically rebased.
Build system: x86_64
Build-tested: ramips/mt7621*
*Had to revert 7f1edbd in order to build due to FS#4149
Signed-off-by: John Audia <graysky@archlinux.us>
84 lines
2.6 KiB
Diff
84 lines
2.6 KiB
Diff
From 53c3bd0d5a873c23841bb95e7b95c1c3630c50bd Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Thu, 12 Jul 2018 13:03:13 +0300
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Subject: [PATCH] at803x: Address packet drops at low traffic rate due to
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SmartEEE feature
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* According to the AR8035 datasheet, smartEEE mode (active by default)
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makes the PHY enters sleep after a configurable idle time. It does
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this autonomously, without LPI (Low Power Idle) signals coming from MAC.
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* Tested with ping (default of 1 second interval) over back-to-back
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RGMII between 2 boards having AR8035 at both ends:
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- Without patch:
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225 packets transmitted, 145 received, 35% packet loss, time 229334ms
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- With patch:
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144 packets transmitted, 144 received, 0% packet loss, time 146378ms
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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---
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drivers/net/phy/Kconfig | 10 ++++++++++
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drivers/net/phy/at803x.c | 22 ++++++++++++++++++++++
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2 files changed, 32 insertions(+)
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -363,6 +363,16 @@ config AT803X_PHY
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---help---
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Currently supports the AT8030 and AT8035 model
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+config AT803X_PHY_SMART_EEE
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+ depends on AT803X_PHY
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+ default n
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+ tristate "SmartEEE feature for AT803X PHYs"
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+ ---help---
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+ Enables the Atheros SmartEEE feature (not IEEE 802.3az). When 2 PHYs
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+ which support this feature are connected back-to-back, they may
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+ negotiate a low-power sleep mode autonomously, without the Ethernet
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+ controller's knowledge. May cause packet loss.
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+
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config BCM63XX_PHY
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tristate "Broadcom 63xx SOCs internal PHY"
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depends on BCM63XX || COMPILE_TEST
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--- a/drivers/net/phy/at803x.c
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+++ b/drivers/net/phy/at803x.c
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@@ -62,6 +62,8 @@
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#define AT803X_DEBUG_REG_5 0x05
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#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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+#define AT803X_LPI_EN BIT(8)
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+
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#define ATH8030_PHY_ID 0x004dd076
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#define ATH8031_PHY_ID 0x004dd074
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#define ATH8032_PHY_ID 0x004dd023
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@@ -299,10 +301,30 @@ static int at803x_probe(struct phy_devic
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return ret;
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}
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+static void at803x_enable_smart_eee(struct phy_device *phydev, int on)
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+{
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+ int value;
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+
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+ /* 5.1.11 Smart_eee control3 */
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+ value = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x805D);
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+ if (on)
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+ value |= AT803X_LPI_EN;
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+ else
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+ value &= ~AT803X_LPI_EN;
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, 0x805D, value);
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+}
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+
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static int at803x_config_init(struct phy_device *phydev)
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{
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int ret;
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+
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+#ifdef CONFIG_AT803X_PHY_SMART_EEE
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+ at803x_enable_smart_eee(phydev, 1);
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+#else
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+ at803x_enable_smart_eee(phydev, 0);
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+#endif
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+
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/* The RX and TX delay default is:
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* after HW reset: RX delay enabled and TX delay disabled
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* after SW reset: RX delay enabled, while TX delay retains the
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