mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 22:47:56 +00:00
0171157d45
The patches were generated from the RPi repo with the following command: git format-patch v6.6.44..rpi-6.6.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
93 lines
4.0 KiB
Diff
93 lines
4.0 KiB
Diff
From 9a108c82b6f6526e0aa8a19befa1ed3f31f8fe52 Mon Sep 17 00:00:00 2001
|
|
From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
|
|
Date: Fri, 10 May 2024 15:42:29 +0100
|
|
Subject: [PATCH 1178/1215] dts: rp1: DSI drivers to use newly defined MIPI
|
|
byte source clocks.
|
|
|
|
Remove the "dummy" 72MHz fixed clock sources and associate DSI driver
|
|
with the new "variable" clock sources now defined in RP1 clocks.
|
|
|
|
Also add PLLSYS clock to DSI, which it will need as an alternative
|
|
clock source in those cases where DPI pixclock > DSI byteclock.
|
|
|
|
Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
|
|
---
|
|
arch/arm/boot/dts/broadcom/rp1.dtsi | 50 +++++++++--------------------
|
|
1 file changed, 15 insertions(+), 35 deletions(-)
|
|
|
|
--- a/arch/arm/boot/dts/broadcom/rp1.dtsi
|
|
+++ b/arch/arm/boot/dts/broadcom/rp1.dtsi
|
|
@@ -1109,16 +1109,15 @@
|
|
|
|
interrupts = <RP1_INT_MIPI0 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
- clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>, // required, config bus clock
|
|
- <&rp1_clocks RP1_CLK_MIPI0_DPI>, // required, pixel clock
|
|
- <&clksrc_mipi0_dsi_byteclk>, // internal, parent for divide
|
|
- <&clk_xosc>; // hardwired to DSI "refclk"
|
|
- clock-names = "cfgclk", "dpiclk", "byteclk", "refclk";
|
|
+ clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>,
|
|
+ <&rp1_clocks RP1_CLK_MIPI0_DPI>,
|
|
+ <&rp1_clocks RP1_CLK_MIPI0_DSI_BYTECLOCK>,
|
|
+ <&clk_xosc>, // hardwired to DSI "refclk"
|
|
+ <&rp1_clocks RP1_PLL_SYS>; // alternate parent for divide
|
|
+ clock-names = "cfgclk", "dpiclk", "byteclk", "refclk", "pllsys";
|
|
|
|
- assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>,
|
|
- <&rp1_clocks RP1_CLK_MIPI0_DPI>;
|
|
+ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>;
|
|
assigned-clock-rates = <25000000>;
|
|
- assigned-clock-parents = <0>, <&clksrc_mipi0_dsi_byteclk>;
|
|
};
|
|
|
|
rp1_dsi1: dsi@128000 {
|
|
@@ -1130,16 +1129,15 @@
|
|
|
|
interrupts = <RP1_INT_MIPI1 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
- clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>, // required, config bus clock
|
|
- <&rp1_clocks RP1_CLK_MIPI1_DPI>, // required, pixel clock
|
|
- <&clksrc_mipi1_dsi_byteclk>, // internal, parent for divide
|
|
- <&clk_xosc>; // hardwired to DSI "refclk"
|
|
- clock-names = "cfgclk", "dpiclk", "byteclk", "refclk";
|
|
+ clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>,
|
|
+ <&rp1_clocks RP1_CLK_MIPI1_DPI>,
|
|
+ <&rp1_clocks RP1_CLK_MIPI1_DSI_BYTECLOCK>,
|
|
+ <&clk_xosc>, // hardwired to DSI "refclk"
|
|
+ <&rp1_clocks RP1_PLL_SYS>; // alternate parent for divide
|
|
+ clock-names = "cfgclk", "dpiclk", "byteclk", "refclk", "pllsys";
|
|
|
|
- assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>,
|
|
- <&rp1_clocks RP1_CLK_MIPI1_DPI>;
|
|
+ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>;
|
|
assigned-clock-rates = <25000000>;
|
|
- assigned-clock-parents = <0>, <&clksrc_mipi1_dsi_byteclk>;
|
|
};
|
|
|
|
/* VEC and DPI both need to control PLL_VIDEO and cannot work together; */
|
|
@@ -1216,24 +1214,6 @@
|
|
clock-output-names = "core";
|
|
clock-frequency = <50000000>;
|
|
};
|
|
- clksrc_mipi0_dsi_byteclk: clksrc_mipi0_dsi_byteclk {
|
|
- // This clock is synthesized by MIPI0 D-PHY, when DSI is running.
|
|
- // Its frequency is not known a priori (until a panel driver attaches)
|
|
- // so assign a made-up frequency of 72MHz so it can be divided for DPI.
|
|
- compatible = "fixed-clock";
|
|
- #clock-cells = <0>;
|
|
- clock-output-names = "clksrc_mipi0_dsi_byteclk";
|
|
- clock-frequency = <72000000>;
|
|
- };
|
|
- clksrc_mipi1_dsi_byteclk: clksrc_mipi1_dsi_byteclk {
|
|
- // This clock is synthesized by MIPI1 D-PHY, when DSI is running.
|
|
- // Its frequency is not known a priori (until a panel driver attaches)
|
|
- // so assign a made-up frequency of 72MHz so it can be divided for DPI.
|
|
- compatible = "fixed-clock";
|
|
- #clock-cells = <0>;
|
|
- clock-output-names = "clksrc_mipi1_dsi_byteclk";
|
|
- clock-frequency = <72000000>;
|
|
- };
|
|
/* GPIO derived clock sources. Each GPIO with a GPCLK function
|
|
* can drive its output from the respective GPCLK
|
|
* generator, and provide a clock source to other internal
|