mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 15:02:32 +00:00
b04f245c39
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.23 Removed upstreamed: pending-6.6/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch[1] pending-6.6/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch[2] mediatek/patches-6.6/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch[3] Manually rebased: mediatek/patches-6.6/100-dts-update-mt7622-rfb1.patch Added: generic/backports-6.6/981-mtd-spinand-Add-support-for-5-byte-IDs.patch[4] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=1f32abb474c1c9bdb21d9eda74c325a0b3a162e5 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=943c14ece95eb1cf98d477462aebcbfdfd714633 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=6ff01b314149d1cf59caebc29384f0beed21cba4 4. See comments in https://github.com/openwrt/openwrt/pull/14992 regarding broken flogic/xiaomi_redmi-router-ax6000-ubootmod Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, flogic/glinet_gl-mt6000 Run-tested: x86/64/AMD Cezannei, flogic/xiaomi_redmi-router-ax6000-ubootmod, flogic/glinet_gl-mt6000 Signed-off-by: John Audia <therealgraysky@proton.me>
131 lines
4.1 KiB
Diff
131 lines
4.1 KiB
Diff
From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
|
|
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
|
Date: Thu, 23 Jun 2022 18:29:51 +0800
|
|
Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
|
|
data
|
|
|
|
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
|
---
|
|
drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
|
|
include/linux/platform_data/spi-mt65xx.h | 17 --------------
|
|
2 files changed, 11 insertions(+), 35 deletions(-)
|
|
delete mode 100644 include/linux/platform_data/spi-mt65xx.h
|
|
|
|
--- a/drivers/spi/spi-mt65xx.c
|
|
+++ b/drivers/spi/spi-mt65xx.c
|
|
@@ -14,7 +14,6 @@
|
|
#include <linux/of.h>
|
|
#include <linux/gpio/consumer.h>
|
|
#include <linux/platform_device.h>
|
|
-#include <linux/platform_data/spi-mt65xx.h>
|
|
#include <linux/pm_runtime.h>
|
|
#include <linux/spi/spi.h>
|
|
#include <linux/spi/spi-mem.h>
|
|
@@ -171,6 +170,8 @@ struct mtk_spi {
|
|
struct device *dev;
|
|
dma_addr_t tx_dma;
|
|
dma_addr_t rx_dma;
|
|
+ u32 sample_sel;
|
|
+ u32 get_tick_dly;
|
|
};
|
|
|
|
static const struct mtk_spi_compatible mtk_common_compat;
|
|
@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
|
|
.no_need_unprepare = true,
|
|
};
|
|
|
|
-/*
|
|
- * A piece of default chip info unless the platform
|
|
- * supplies it.
|
|
- */
|
|
-static const struct mtk_chip_config mtk_default_chip_info = {
|
|
- .sample_sel = 0,
|
|
- .tick_delay = 0,
|
|
-};
|
|
-
|
|
static const struct of_device_id mtk_spi_of_match[] = {
|
|
{ .compatible = "mediatek,spi-ipm",
|
|
.data = (void *)&mtk_ipm_compat,
|
|
@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
|
|
{
|
|
u16 cpha, cpol;
|
|
u32 reg_val;
|
|
- struct mtk_chip_config *chip_config = spi->controller_data;
|
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
|
|
|
cpha = spi->mode & SPI_CPHA ? 1 : 0;
|
|
@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
|
|
else
|
|
reg_val &= ~SPI_CMD_CS_POL;
|
|
|
|
- if (chip_config->sample_sel)
|
|
+ if (mdata->sample_sel)
|
|
reg_val |= SPI_CMD_SAMPLE_SEL;
|
|
else
|
|
reg_val &= ~SPI_CMD_SAMPLE_SEL;
|
|
@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
|
|
if (mdata->dev_comp->ipm_design) {
|
|
reg_val = readl(mdata->base + SPI_CMD_REG);
|
|
reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
|
|
- reg_val |= ((chip_config->tick_delay & 0x7)
|
|
+ reg_val |= ((mdata->get_tick_dly & 0x7)
|
|
<< SPI_CMD_IPM_GET_TICKDLY_OFFSET);
|
|
writel(reg_val, mdata->base + SPI_CMD_REG);
|
|
} else {
|
|
reg_val = readl(mdata->base + SPI_CFG1_REG);
|
|
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
|
|
- reg_val |= ((chip_config->tick_delay & 0x7)
|
|
+ reg_val |= ((mdata->get_tick_dly & 0x7)
|
|
<< SPI_CFG1_GET_TICK_DLY_OFFSET);
|
|
writel(reg_val, mdata->base + SPI_CFG1_REG);
|
|
}
|
|
} else {
|
|
reg_val = readl(mdata->base + SPI_CFG1_REG);
|
|
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
|
|
- reg_val |= ((chip_config->tick_delay & 0x3)
|
|
+ reg_val |= ((mdata->get_tick_dly & 0x3)
|
|
<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
|
|
writel(reg_val, mdata->base + SPI_CFG1_REG);
|
|
}
|
|
@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
|
|
{
|
|
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
|
|
|
|
- if (!spi->controller_data)
|
|
- spi->controller_data = (void *)&mtk_default_chip_info;
|
|
-
|
|
if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0))
|
|
/* CS de-asserted, gpiolib will handle inversion */
|
|
gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
|
|
@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform
|
|
mdata = spi_master_get_devdata(master);
|
|
mdata->dev_comp = device_get_match_data(dev);
|
|
|
|
+ /* Set device configs to default first. Calibrate it later. */
|
|
+ mdata->sample_sel = 0;
|
|
+ mdata->get_tick_dly = 2;
|
|
+
|
|
if (mdata->dev_comp->enhance_timing)
|
|
master->mode_bits |= SPI_CS_HIGH;
|
|
|
|
--- a/include/linux/platform_data/spi-mt65xx.h
|
|
+++ /dev/null
|
|
@@ -1,17 +0,0 @@
|
|
-/* SPDX-License-Identifier: GPL-2.0-only */
|
|
-/*
|
|
- * MTK SPI bus driver definitions
|
|
- *
|
|
- * Copyright (c) 2015 MediaTek Inc.
|
|
- * Author: Leilk Liu <leilk.liu@mediatek.com>
|
|
- */
|
|
-
|
|
-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
|
-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
|
-
|
|
-/* Board specific platform_data */
|
|
-struct mtk_chip_config {
|
|
- u32 sample_sel;
|
|
- u32 tick_delay;
|
|
-};
|
|
-#endif
|