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518 lines
12 KiB
C
518 lines
12 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Thomas Langer, Ralph Hempel
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/addrspace.h>
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#include <asm/danube.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_HTTPD)
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#include <httpd.h>
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#endif
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#if defined(CONFIG_AR8216_SWITCH)
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#include "athrs26_phy.h"
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#endif
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extern ulong ifx_get_ddr_hz(void);
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extern ulong ifx_get_cpuclk(void);
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/* IDs and registers of known external switches */
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void _machine_restart(void)
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{
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*DANUBE_RCU_RST_REQ |=1<<30;
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}
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#ifdef CONFIG_SYS_RAMBOOT
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phys_size_t initdram(int board_type)
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{
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return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
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}
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#elif defined(CONFIG_USE_DDR_RAM)
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phys_size_t initdram(int board_type)
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{
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return (CONFIG_SYS_MAX_RAM);
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}
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#else
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static ulong max_sdram_size(void) /* per Chip Select */
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{
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/* The only supported SDRAM data width is 16bit.
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*/
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#define CFG_DW 4
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/* The only supported number of SDRAM banks is 4.
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*/
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#define CFG_NB 4
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ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
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int cols = cfgpb0 & 0xF;
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int rows = (cfgpb0 & 0xF0) >> 4;
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ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
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return size;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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static long int dram_size(long int *base, long int maxsize)
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{
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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phys_size_t initdram(int board_type)
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{
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int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
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ulong size, max_size = 0;
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ulong our_address;
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/* load t9 into our_address */
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asm volatile ("move %0, $25" : "=r" (our_address) :);
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/* Can't probe for RAM size unless we are running from Flash.
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* find out whether running from DRAM or Flash.
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*/
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if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
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{
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return max_sdram_size();
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}
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for (cols = 0x8; cols <= 0xC; cols++)
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{
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for (rows = 0xB; rows <= 0xD; rows++)
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{
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*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
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(rows << 4) | cols;
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size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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max_sdram_size());
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if (size > max_size)
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{
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best_val = *DANUBE_SDRAM_MC_CFGPB0;
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max_size = size;
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}
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}
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}
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*DANUBE_SDRAM_MC_CFGPB0 = best_val;
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return max_size;
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}
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#endif
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static void gpio_default(void)
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{
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#ifdef CONFIG_SWITCH_PORT0
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*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P0_OD |= (1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P0_DIR |= (1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P0_OUT |= (1<<CONFIG_SWITCH_PIN);
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#elif defined(CONFIG_SWITCH_PORT1)
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*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P1_OD |= (1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P1_DIR |= (1<<CONFIG_SWITCH_PIN);
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*DANUBE_GPIO_P1_OUT |= (1<<CONFIG_SWITCH_PIN);
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#endif
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#ifdef CONFIG_EBU_GPIO
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{
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int i = 0;
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printf ("bring up ebu gpio\n");
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*DANUBE_EBU_BUSCON1 = 0x1e7ff;
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*DANUBE_EBU_ADDSEL1 = 0x14000001;
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*((volatile u16*)0xb4000000) = 0x0;
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for(i = 0; i < 1000; i++)
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udelay(1000);
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*((volatile u16*)0xb4000000) = CONFIG_EBU_GPIO;
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*DANUBE_EBU_BUSCON1 = 0x8001e7ff;
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}
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#endif
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#ifdef CONFIG_BUTTON_PORT0
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*DANUBE_GPIO_P0_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
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*DANUBE_GPIO_P0_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
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*DANUBE_GPIO_P0_DIR &= ~(1<<CONFIG_BUTTON_PIN);
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if(!!(*DANUBE_GPIO_P0_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
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{
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printf("button is pressed\n");
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setenv("bootdelay", "0");
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setenv("bootcmd", "httpd");
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}
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#elif defined(CONFIG_BUTTON_PORT1)
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*DANUBE_GPIO_P1_ALTSEL0 &= ~(1<<CONFIG_BUTTON_PIN);
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*DANUBE_GPIO_P1_ALTSEL1 &= ~(1<<CONFIG_BUTTON_PIN);
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*DANUBE_GPIO_P1_DIR &= ~(1<<CONFIG_BUTTON_PIN);
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if(!!(*DANUBE_GPIO_P1_IN & (1<<CONFIG_BUTTON_PIN)) == CONFIG_BUTTON_LEVEL)
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{
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printf("button is pressed\n");
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setenv("bootdelay", "0");
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setenv("bootcmd", "httpd");
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}
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#endif
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#ifdef CONFIG_ARV4525
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*DANUBE_GPIO_P0_ALTSEL0 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
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*DANUBE_GPIO_P0_ALTSEL1 &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
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*DANUBE_GPIO_P0_OD |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
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*DANUBE_GPIO_P0_DIR |= ((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
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*DANUBE_GPIO_P0_OUT &= ~((1<<4)|(1<<5)|(1<<6)|(1<<8)|(1<<9));
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#endif
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}
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int checkboard (void)
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{
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unsigned long chipid = *DANUBE_MPS_CHIPID;
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int part_num;
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puts ("Board: "CONFIG_ARCADYAN"\n");
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puts ("SoC: ");
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part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
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switch (part_num)
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{
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case 0x129:
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case 0x12D:
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case 0x12b:
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puts("Danube/Twinpass/Vinax-VE ");
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break;
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default:
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printf ("unknown, chip part number 0x%03X ", part_num);
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break;
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}
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printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
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printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
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printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
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return 0;
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}
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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int board_early_init_f(void)
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{
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#ifdef CONFIG_EBU_ADDSEL0
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(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
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#endif
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#ifdef CONFIG_EBU_ADDSEL1
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(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
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#endif
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#ifdef CONFIG_EBU_ADDSEL2
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(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
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#endif
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#ifdef CONFIG_EBU_ADDSEL3
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(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
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#endif
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#ifdef CONFIG_EBU_BUSCON0
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(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
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#endif
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#ifdef CONFIG_EBU_BUSCON1
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(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
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#endif
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#ifdef CONFIG_EBU_BUSCON2
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(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
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#endif
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#ifdef CONFIG_EBU_BUSCON3
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(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
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#endif
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return 0;
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#ifdef CONFIG_RTL8306_SWITCH
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#define ID_RTL8306 0x5988
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static int external_switch_rtl8306(void)
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{
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unsigned short chipid;
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static char * const name = "lq_cpe_eth";
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udelay(100000);
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puts("\nsearching for rtl8306 switch ... ");
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if (miiphy_read(name, 4, 30, &chipid) == 0) {
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if (chipid == ID_RTL8306) {
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puts("found");
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/* set led mode */
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miiphy_write(name, 0, 19, 0xffff);
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/* magic */
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miiphy_write(name, 4, 22, 0x877f);
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puts("\n");
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return 0;
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}
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puts("failed\n");
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}
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puts("\nno known switch found ... \n");
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return 0;
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}
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#endif
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#ifdef CONFIG_RTL8306G_SWITCH
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#define ID_RTL8306 0x5988
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static int external_switch_rtl8306G(void)
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{
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unsigned short chipid,val;
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int i;
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static char * const name = "lq_cpe_eth";
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unsigned int chipid2, chipver, chiptype;
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char str[128];
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int cpu_mask = 1 << 5;
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udelay(100000);
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puts("\nsearching for rtl8306 switch ... ");
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if (miiphy_read(name, 4, 30, &chipid) == 0) {
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if (chipid == ID_RTL8306) {
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puts("found\nReset Hard\n");
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#ifdef CONFIG_ARV752DPW
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//gpio 19
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//reset reset ping to high
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*DANUBE_GPIO_P1_DIR |= 8;
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*DANUBE_GPIO_P1_OUT |= 8;
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udelay(500*1000);
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*DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
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udelay(500*1000);
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*DANUBE_GPIO_P1_OUT |= 8;
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udelay(500*1000);
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puts("Done\n");
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#endif
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/* set led mode */
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miiphy_write(name, 0, 0, 0x3100);
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miiphy_write(name, 0, 18, 0x7fff);
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miiphy_write(name, 0, 19, 0xffff);
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miiphy_write(name, 0, 22, 0x877f);
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miiphy_write(name, 0, 24, 0x0ed1);
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miiphy_write(name, 1, 0, 0x3100);
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miiphy_write(name, 1, 22, 0x877f);
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miiphy_write(name, 1, 24, 0x1ed2);
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miiphy_write(name, 2, 0, 0x3100);
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miiphy_write(name, 2, 22, 0x877f);
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miiphy_write(name, 2, 23, 0x0020);
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miiphy_write(name, 2, 24, 0x2ed4);
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miiphy_write(name, 3, 0, 0x3100);
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miiphy_write(name, 3, 22, 0x877f);
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miiphy_write(name, 3, 24, 0x3ed8);
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miiphy_write(name, 4, 0, 0x3100);
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miiphy_write(name, 4, 22, 0x877f);
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miiphy_write(name, 4, 24, 0x4edf);
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miiphy_write(name, 5, 0, 0x3100);
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miiphy_write(name, 6, 0, 0x2100);
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//important. enable phy 5 link status, for rmii
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miiphy_write(name, 6, 22, 0x873f);
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miiphy_write(name, 6, 24, 0x8eff);
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//disable ports
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for (i=0;i<5;i++) {
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miiphy_read(name, 0, 24, &val);
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val&=~(1<<10);
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val&=~(1<<11);
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miiphy_write(name, 0, 24, val);
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}
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puts("Reset Soft\n");
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miiphy_write(name,0 ,0 ,1<<15);
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for (i=0;i<1000;i++)
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{
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miiphy_read(name,0 ,0 ,&val);
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if (!(val&1<<15))
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break;
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udelay(1000);
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}
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if (i==1000)
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puts("Failed\n");
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else
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puts("Success\n");
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//enable ports egain
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for (i=0;i<5;i++) // enable ports
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{
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miiphy_read(name, 0, 24, &val);
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val|=(1<<10);
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val|=(1<<11);
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miiphy_write(name, 0, 24, val);
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}
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puts("\n");
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return 0;
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}
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puts("failed\n");
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}
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puts("\nno known switch found ... \n");
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return 0;
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}
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#endif
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#ifdef CONFIG_AR8216_SWITCH
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static int external_switch_ar8216(void)
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{
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puts("initializing ar8216 switch... ");
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if (athrs26_phy_setup(0)==0) {
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printf("initialized\n");
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return 0;
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}
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puts("failed ... \n");
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return 0;
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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gpio_default();
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#if defined(CONFIG_IFX_ETOP)
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uchar enetaddr[6];
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if (!eth_getenv_enetaddr("ethaddr", enetaddr))
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eth_setenv_enetaddr("ethaddr", (uchar *)0xb03f0016);
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*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
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*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
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if (lq_eth_initialize(bis))
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return -1;
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*DANUBE_RCU_RST_REQ |=1;
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udelay(200000);
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*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
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udelay(1000);
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#ifdef CONFIG_RTL8306G_SWITCH
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if (external_switch_rtl8306G()<0)
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return -1;
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#endif
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#ifdef CONFIG_RTL8306_SWITCH
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if (external_switch_rtl8306()<0)
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return -1;
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#endif
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#ifdef CONFIG_AR8216_SWITCH
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if (external_switch_ar8216()<0)
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return -1;
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#endif
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#endif
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return 0;
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}
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#if defined(CONFIG_CMD_HTTPD)
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int do_http_upgrade(const unsigned char *data, const ulong size)
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{
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char buf[128];
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if(getenv ("ram_addr") == NULL)
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return -1;
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if(getenv ("kernel_addr") == NULL)
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return -1;
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/* check the image */
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if(run_command("imi ${ram_addr}", 0) < 0) {
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return -1;
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}
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/* write the image to the flash */
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puts("http ugrade ...\n");
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sprintf(buf, "era ${kernel_addr} +0x%lx; cp.b ${ram_addr} ${kernel_addr} 0x%lx", size, size);
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return run_command(buf, 0);
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}
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int do_http_progress(const int state)
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{
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/* toggle LED's here */
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switch(state) {
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case HTTP_PROGRESS_START:
|
|
puts("http start\n");
|
|
break;
|
|
case HTTP_PROGRESS_TIMEOUT:
|
|
puts(".");
|
|
break;
|
|
case HTTP_PROGRESS_UPLOAD_READY:
|
|
puts("http upload ready\n");
|
|
break;
|
|
case HTTP_PROGRESS_UGRADE_READY:
|
|
puts("http ugrade ready\n");
|
|
break;
|
|
case HTTP_PROGRESS_UGRADE_FAILED:
|
|
puts("http ugrade failed\n");
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
unsigned long do_http_tmp_address(void)
|
|
{
|
|
char *s = getenv ("ram_addr");
|
|
if (s) {
|
|
ulong tmp = simple_strtoul (s, NULL, 16);
|
|
return tmp;
|
|
}
|
|
return 0 /*0x80a00000*/;
|
|
}
|
|
|
|
#endif
|