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9a038e7fd1
Copy config and patches from kernel 5.10 to kernel 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
118 lines
3.6 KiB
Diff
118 lines
3.6 KiB
Diff
From 7f353accca6e4a3222991c65b1a6801503973bd3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 2 Jul 2021 16:44:10 +0200
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Subject: [PATCH] PCI: aardvark: Add support for masking MSI interrupts
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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We should not unmask MSIs at setup, but only when kernel asks for them
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to be unmasked.
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At setup, mask all MSIs, and implement IRQ chip callbacks for masking
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and unmasking particular MSIs.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 54 ++++++++++++++++++++++++---
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1 file changed, 49 insertions(+), 5 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -281,6 +281,7 @@ struct advk_pcie {
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raw_spinlock_t irq_lock;
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struct irq_domain *msi_domain;
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struct irq_domain *msi_inner_domain;
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+ raw_spinlock_t msi_irq_lock;
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DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
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struct mutex msi_used_lock;
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u16 msi_msg;
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@@ -577,12 +578,10 @@ static void advk_pcie_setup_hw(struct ad
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
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advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
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- /* Disable All ISR0/1 Sources */
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+ /* Disable All ISR0/1 and MSI Sources */
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advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
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advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
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-
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- /* Unmask all MSIs */
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- advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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+ advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
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/* Unmask summary MSI interrupt */
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reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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@@ -1198,10 +1197,52 @@ static int advk_msi_set_affinity(struct
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return -EINVAL;
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}
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+static void advk_msi_irq_mask(struct irq_data *d)
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+{
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+ struct advk_pcie *pcie = d->domain->host_data;
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+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
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+ unsigned long flags;
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+ u32 mask;
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+
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+ raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
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+ mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
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+ mask |= BIT(hwirq);
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+ advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
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+ raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
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+}
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+
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+static void advk_msi_irq_unmask(struct irq_data *d)
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+{
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+ struct advk_pcie *pcie = d->domain->host_data;
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+ irq_hw_number_t hwirq = irqd_to_hwirq(d);
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+ unsigned long flags;
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+ u32 mask;
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+
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+ raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
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+ mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
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+ mask &= ~BIT(hwirq);
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+ advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
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+ raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
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+}
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+
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+static void advk_msi_top_irq_mask(struct irq_data *d)
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+{
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+ pci_msi_mask_irq(d);
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+ irq_chip_mask_parent(d);
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+}
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+
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+static void advk_msi_top_irq_unmask(struct irq_data *d)
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+{
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+ pci_msi_unmask_irq(d);
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+ irq_chip_unmask_parent(d);
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+}
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+
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static struct irq_chip advk_msi_bottom_irq_chip = {
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.name = "MSI",
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.irq_compose_msi_msg = advk_msi_irq_compose_msi_msg,
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.irq_set_affinity = advk_msi_set_affinity,
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+ .irq_mask = advk_msi_irq_mask,
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+ .irq_unmask = advk_msi_irq_unmask,
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};
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static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
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@@ -1291,7 +1332,9 @@ static const struct irq_domain_ops advk_
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};
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static struct irq_chip advk_msi_irq_chip = {
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- .name = "advk-MSI",
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+ .name = "advk-MSI",
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+ .irq_mask = advk_msi_top_irq_mask,
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+ .irq_unmask = advk_msi_top_irq_unmask,
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};
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static struct msi_domain_info advk_msi_domain_info = {
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@@ -1305,6 +1348,7 @@ static int advk_pcie_init_msi_irq_domain
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struct device *dev = &pcie->pdev->dev;
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phys_addr_t msi_msg_phys;
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+ raw_spin_lock_init(&pcie->msi_irq_lock);
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mutex_init(&pcie->msi_used_lock);
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msi_msg_phys = virt_to_phys(&pcie->msi_msg);
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